CS4351
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT
(Inputs: Logic 0 = GND, Logic 1 = VL, C = 20 pF)
L
Parameter
Symbol
Min
Max
Unit
CCLK Clock Frequency
f
-
6
MHz
sclk
RST Rising Edge to CS Falling
CCLK Edge to CS Falling
CS High Time Between Transmissions
CS Falling to CCLK Edge
CCLK Low Time
t
500
500
1.0
20
66
66
40
15
-
-
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
srs
(Note 8)
t
-
spi
t
-
csh
t
-
css
t
-
scl
sch
dsu
CCLK High Time
t
-
-
CDIN to CCLK Rising Setup Time
CCLK Rising to DATA Hold Time
Rise Time of CCLK and CDIN
Fall Time of CCLK and CDIN
t
(Note 9)
(Note 10)
(Note 10)
t
-
dh
t
100
100
r2
t
-
f2
Notes: 8. t only needed before first falling edge of CS after RST rising edge. t = 0 at all other times.
spi
spi
9. Data must be held for sufficient time to bridge the transition time of CCLK.
10. For F < 1 MHz.
SCK
RST
t
t
srs
spi
CS
t
t
t
css
scl
sch
t
csh
CCLK
t
t
r2
f2
C DIN
t
t
dsu
dh
Figure 3. Control Port Timing - SPI Format (Write)
DS566PP2
13
CIRRUS [ CIRRUS LOGIC ]
