CS4351
4.2 System Clocking
The device requires external generation of the master (MCLK), left/right (LRCK) and serial (SCLK)
clocks. The left/right clock, defined also as the input sample rate (F ), must be synchronously derived from
s
the MCLK according to specified ratios. The specified ratios of MCLK to LRCK, along with several stan-
dard audio sample rates and the required MCLK frequency, are illustrated in Tables 4-6.
Refer to section 4.3 for the required SCLK timing associated with the selected Digital Interface Format,
and SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE, page 11 for the maximum allowed
clock frequencies.
Sample Rate
(kHz)
MCLK (MHz)
256x
384x
512x
768x
1024x
32.7680
45.1584
49.1520
1152x
36.8640
32
44.1
48
8.1920
11.2896
12.2880
12.2880
16.9344
18.4320
16.3840
22.5792
24.5760
24.5760
33.8688
36.8640
Table 4. Single-Speed Mode Standard Frequencies
Sample Rate
(kHz)
MCLK (MHz)
128x
192x
256x
384x
512x
64
88.2
96
8.1920
11.2896
12.2880
12.2880
16.9344
18.4320
16.3840
22.5792
24.5760
24.5760
33.8688
36.8640
32.7680
45.1584
49.1520
Table 5. Double-Speed Mode Standard Frequencies
Sample Rate
(kHz)
MCLK (MHz)
64x
96x
128x
192x
256x
176.4
192
11.2896
12.2880
16.9344
18.4320
22.5792
24.5760
33.8688
36.8640
45.1584
49.1520
Table 6. Quad-Speed Mode Standard Frequencies
= Denotes clock modes which are NOT auto detected
DS566PP2
17
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