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CS4297A-JQEP 参数 Datasheet PDF下载

CS4297A-JQEP图片预览
型号: CS4297A-JQEP
PDF下载: 下载PDF文件 查看货源
内容描述: [Consumer Circuit, PQFP48, 9 X 9 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, MS-022, TQFP-48]
分类和应用: 解码器编解码器
文件页数/大小: 46 页 / 897 K
品牌: CIRRUS [ CIRRUS LOGIC ]
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CS4297  
CrystalClear™ SoundFusion™ Audio Codec ’97  
AC’97 Controller. The data format for the input  
frame is very similar to the output frame. Synchro-  
nization of the CS4297 to the AC’97 Controller is  
performed in the same manner. Please refer to Fig-  
ure 3 for the serial port timing waveform.  
AC-Link Audio Input Frame  
An AC-Link serial data input frame uses the  
SYNC, BIT_CLK, and SDATA_IN signals are  
used. In the serial data input frame, data is passed  
on the SDATA_IN pin FROM the CS4297 TO the  
Slot 0: Serial Data Input Slot Tag Bits  
The first slot, Slot 0, is a 16-bit slot which contains information about the validity of data for the remaining  
12 slots. The 16 bits of this slot are defined as:  
F0  
Bit 15  
F1  
14  
F2  
13  
F3  
12  
F4  
11  
F5  
10  
F6  
9
F7  
8
F8  
7
F9  
6
F10  
5
F11  
4
F12  
3
F13  
2
F14  
1
F15  
0
Codec Slot 1 Slot 2 Slot 3 Slot 4  
Ready Valid Valid Valid Valid  
Not Used  
Codec Ready - Bit 15 indicates the readiness of the CS4297’s AC-Link and the AC’97 Control and Status  
Registers. Immediately after a Cold Reset this bit will be returned to the AC’97 Controller ‘cleared’. Once  
the CS4297’s clocks and voltages are stable, this bit will be set. Until the Codec Ready bit is ‘set’, no AC-  
Link transactions should be attempted by the AC’97 Controller.  
NOTE: This Codec Ready bit does not indicate readiness of the DACs, ADCs, Vref, or any other analog  
function. Those must be checked in the Powerdown/Status Register by the AC’97 Controller. Any accesses  
to the CS4297 while this bit is ‘cleared’ will be ignored.  
Slot 1 Valid - Bit 14 indicates the validity of data in the serial data input Slot 1. If this bit is ‘set’, Slot 1  
contains valid data. If this bit is ‘cleared’, Slot 1 should be ignored by the AC’97 Controller.  
Slot 2 Valid - Bit 13 indicates the validity of data in the serial data input Slot 2. If this bit is ‘set’, Slot 2  
contains valid data. If this bit is ‘cleared’, Slot 2 should be ignored by the AC’97 Controller.  
Slot 3 Valid - Bit 12 indicates the validity of data in the serial data input Slot 3. If this bit is ‘set’, Slot 3  
contains valid data. If this bit is ‘cleared’, Slot 3 should be ignored by the AC’97 Controller.  
Slot 4 Valid - Bit 11 indicates the validity of data in the serial data input Slot 4. If this bit is ‘set’, Slot 4  
contains valid data. If this bit is ‘cleared’, Slot 4 should be ignored by the AC’97 Controller.  
Slot 0 bits 10 through 0 represent unimplemented data slots in the CS4297 and should be ignored by the  
AC’97 Controller.  
18  
DS242F5  
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