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CS4297A-JQEP 参数 Datasheet PDF下载

CS4297A-JQEP图片预览
型号: CS4297A-JQEP
PDF下载: 下载PDF文件 查看货源
内容描述: [Consumer Circuit, PQFP48, 9 X 9 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, MS-022, TQFP-48]
分类和应用: 解码器编解码器
文件页数/大小: 46 页 / 897 K
品牌: CIRRUS [ CIRRUS LOGIC ]
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CS4297  
CrystalClear™ SoundFusion™ Audio Codec ’97  
tion in a new serial data frame is F0 and the last bit  
position in the serial data frame is F255.  
DIGITAL HARDWARE DESCRIPTION  
AC’97 AC-Link  
When SYNC goes active (high) and is sampled ac-  
tive by the CS4297 (on the falling edge of  
BIT_CLK), both devices are synchronized to a new  
serial data frame. The data on the SDATA_OUT  
pin at this clock edge is the final bit of the previous  
serial data frame’s data. On the next rising edge of  
BIT_CLK, the first bit of slot 0 is driven by the  
AC’97 Controller on the SDATA_OUT pin. The  
CS4297 latches in this data, as the first bit of the  
frame, on the next falling edge of the BIT_CLK  
clock signal.  
The AC-Link is the serial connection between the  
AC’97 Controller and the CS4297. The interface  
consists of 5 signal lines (2 data, 2 clocks, and 1 re-  
set). The basic connections of the link are shown in  
Figure 2. The signals will be explained in detail be-  
low.  
AC-Link Protocol  
The CS4297 serial interface is designed according  
to the AC’97 Specification to allow connection to  
any AC’97 Controller. An AC-Link audio frame is  
divided into 13 ‘slots’; 1 16-bit slot and 12 20-bit  
slots. During each audio frame, data is passed bi-di-  
rectionally between the CS4297 and the AC’97  
Controller.  
DigitalAC’97  
Controller  
CS4297  
SYNC  
BIT_CLK  
AC-Link Serial Data Output Frame  
SDATA_OUT  
For the serial data output frame, the SYNC,  
BIT_CLK, and SDATA_OUT signals are used. In  
the serial data output frame, data is passed on the  
SDATA_OUT pin FROM the AC’97 Controller  
TO the CS4297. In Figure 3 and in the following  
Frame Slot definitions, the position of each bit lo-  
cation within the frame is noted. The first bit posi-  
SDATA_IN  
RESET#  
Figure 2. AC-link Connections  
20.8uS  
(48 KHz)  
Tag Phase  
Data Phase  
SYNC  
12.288 MHz  
81.4 nS  
BIT_CLK  
Bit Frame  
Position  
F255  
X
F0  
F1  
F2  
F12  
X
F13  
X
F14  
X
F15  
X
F16  
R/W  
F36  
F37  
F56 F57  
LP17 LP16  
F76  
F97  
X
F255  
X
Valid  
Frame  
Slot 1  
Valid  
Slot 2  
Valid  
WD15  
WD14  
RP17  
SDATA_OUT  
Bit Frame  
Position  
F255  
0
F0  
F1  
F2  
F12  
0
F13  
0
F14  
0
F15  
0
F16  
0
F36  
F37  
F56 F57  
F76  
F97  
0
F255  
0
Codec  
Ready  
Slot 1  
Valid  
Slot 2  
Valid  
RD15  
RD14  
LC17  
LC16  
RC17  
SDATA_IN  
Slot 0  
Slot 1  
Slot 2  
Slot 3  
Slot 4  
Slots 5-12  
Figure 3. AC-Link Input and Output Framing  
DS242F5  
15  
 
 
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