CS4297
CrystalClear™ SoundFusion™ Audio Codec ’97
AC-Link Reset Modes
AC’97 Register Reset
There are 3 methods to reset the CS4297. These are
defined in the AC’97 Specification as ‘Cold AC’97
Reset’, ‘Warm AC’97 Reset’, and AC’97 Register
Reset. A ‘Cold AC’97 Reset’ is required to restart
the AC-Link when bit PR5 is ‘set’ in register
(0x26).
The third reset mode provides a register reset to the
CS4297. This is available only when the CS4297’s
AC-Link is active and the Codec Ready bit is ‘set’.
The Register Reset allows all user accessible regis-
ters in the CS4297 to be reset to their default, pow-
er-up values. A Register Reset occurs when any
value is written to AC’97 Register 00h.
Cold AC’97 Reset
AC-Link Protocol Violation - Loss of SYNC
A Cold Reset is performed simply by asserting RE-
SET# in accordance with the minimum timing The CS4297 was designed to handle SYNC proto-
specifications in the Serial Port Timing section of col violations. The following are situations where
the data sheet. Once de-asserted, all of the AC’97
Registers will be reset to their default power-on
states and the BIT_CLK clock and SDATA_IN
signals will be reactivated. The timing of power-
up/reset events is discussed in detail in the Power
Management section of the data sheet.
the SYNC protocol has been violated:
The SYNC signal is not sampled high for exactly
16 BIT_CLK clock cycles at the start of an audio
frame.
The SYNC signal is not sampled high on the 256th
BIT_CLK clock period after the previous SYNC
assertion.
Warm AC’97 Reset
The CS4297 may also be reactivated when the AC-
Link is powered down (refer to the PR4 bit descrip-
tion in the Power Management section of the data
sheet) by a Warm Reset. A Warm Reset allows the
AC-Link to be reactivated without losing informa-
tion in the AC’97 Registers. Warm Reset is initiat-
ed when the SYNC signal is driven high for at least
1 µs and then driven low in the absence of the
BIT_CLK clock signal. The BIT_CLK clock will
not restart until at least 2 normal BIT_CLK clock
periods (± 162.8 ns) after the SYNC signal is de-as-
serted.
The SYNC signal goes active high before the 256th
BIT_CLK clock period after the previous SYNC
assertion.
Upon loss of synchronization with the AC’97 Con-
troller, the CS4297 will mute all analog outputs and
‘clear’ the Codec Ready bit in the serial data input
frame until 2 valid frames are detected. During this
detection period, the CS4297 will ignore all regis-
ter reads and writes and will discontinue the trans-
mission of PCM capture data.
DS242F5
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CIRRUS [ CIRRUS LOGIC ]
