No Power
1. VQ = ?
2. Aout bias = ?
3. No audio signal
generated.
Power-Down Mode
1. VQ = 0 V.
2. Aout bias = VQ.
3. No audio signal generated.
4. Control Port Registers retain
settings.
Yes
PDN bit = '1'b?
No
Power-Down (Power Applied)
1. VQ = 0 V.
2. Aout = VQ.
PopGuard®
3. No audio signal generated.
4. Control Port Registers reset
to default.
Power-Up Ramp
Power-Down Ramp
1. VQ ramp down to 0 V.
2. Aout bias = VQ.
250 ms delay
1. VQ ramp up to VA/2.
2. Aout bias = VQ.
400 ms delay
Yes
RST = Low?
No
Control Port
Active
Sub-Clocks Applied
1. LRCK valid.
2. SCLK valid.
3. Audio samples
processed.
Control Port
No
Yes
Access Detected?
No
Valid
MCLK/LRCK
Ratio?
Hardware Mode not supported.
Codec will power up in an
unknown state once all clocks
and data are valid. It is
recommended that the user
setup up the codec via the
control port before applying
MCLK.
Software Mode
Registers setup to
desired settings.
Yes
No Power Transition
1. VQ = 0 V.
No
2. Aout bias = VQ.
3. Audible pops.
Valid MCLK
Applied?
2000 LRCK delay
Yes
Power-Down Transition
1. VQ = 0 V.
2. Aout bias = VQ.
3. Audible pops.
PDN bit set
to '1'b
RST = Low
Normal Operation
1. VQ = VA/2.
2. Aout bias = VQ.
3. Audio signal generated per register settings.
ERROR: Power removed
ERROR: MCLK/LRCK ratio change
ERROR: MCLK removed
Analog Output Mute
1. VQ = VA/2.
Analog Output Freeze
1. VQ = VA/2.
2. Aout bias = VQ.
3. DAC outputs muted.
4. No audio signal generated.
2. Aout bias = VQ + last audio sample.
3. DAC Modulators stop operation.
4. Audible pops.
Figure 12. Audio Output Initialization Flow Chart
DS648PP2
29
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