SWITCHING SPECIFICATIONS - CONTROL PORT - SPI FORMAT
(VLC = 1.8 V - 5.0 V, VLS = VD = 3.3 V, VA = 5.0 V; Inputs: Logic 0 = DGND, Logic 1 = VLC, CDOUT C = 30 pF)
L
Parameter
Symbol
Min
0
Max
6.0
-
Units
MHz
ns
CCLK Clock Frequency
f
sck
t
20
RST Rising Edge to CS Falling
CS Falling to CCLK Edge
CS High Time Between Transmissions
CCLK Low Time
srs
t
t
20
1.0
66
66
40
15
-
-
-
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
css
csh
t
-
scl
sch
dsu
CCLK High Time
t
-
CDIN to CCLK Rising Setup Time
CCLK Rising to DATA Hold Time
CCLK Falling to CDOUT Stable
Rise Time of CDOUT
t
-
(Note 22)
t
t
-
dh
pd
50
25
25
100
100
t
-
r1
Fall Time of CDOUT
t
-
f1
r2
Rise Time of CCLK and CDIN
Fall Time of CCLK and CDIN
(Note 23)
(Note 23)
t
-
t
-
f2
Notes: 22. Data must be held for sufficient time to bridge the transition time of CCLK.
23. For f <1 MHz.
sck
RST
CS
tsrs
tcsh
tcss
tsch
tscl
tr2
CCLK
tf2
tdsu
tdh
MSB
CDIN
tpd
MSB
CDOUT
Figure 8. Control Port Timing - SPI Format
24
DS646PP2
CIRRUS [ CIRRUS LOGIC ]
