SWITCHING SPECIFICATIONS - ADC/DAC PORT (Inputs: Logic 0 = DGND, Logic 1 = VLS,
ADC_SDOUT C
= 15 pF.)
LOAD
Parameters
Symbol
Min
Max
Units
Slave Mode
RST pin Low Pulse Width
MCLK Frequency
(Note 16)
(Note 17)
1
-
ms
MHz
%
0.512
45
50
55
MCLK Duty Cycle
Input Sample Rate (FS pin)
Single-Speed Mode
Double-Speed Mode (Note 18)
Quad-Speed Mode (Note 19)
F
F
F
4
50
100
50
100
200
kHz
kHz
kHz
s
s
s
SCLK Duty Cycle
SCLK High Time
SCLK Low Time
45
8
55
-
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
sckh
t
8
-
sckl
FS Rising Edge to SCLK Rising Edge
t
5
-
fss
fsh
SCLK Rising Edge to FS Falling Edge
t
16
3
-
DAC_SDIN Setup Time Before SCLK Rising Edge
DAC_SDIN Hold Time After SCLK Rising Edge
DAC_SDIN Hold Time After SCLK Rising Edge
ADC_SDOUT Hold Time After SCLK Rising Edge
ADC_SDOUT Valid Before SCLK Rising Edge
t
-
ds
dh
t
5
-
t
t
5
-
dh1
dh2
dval
10
15
-
t
-
Notes: 16. After powering up the CS42438, RST should be held low after the power supplies and clocks are settled.
17. See Table 7 on page 44 for suggested MCLK frequencies.
18. VLS is limited to nominal 2.5 V to 5.0 V operation only.
19. ADC does not meet timing specification for Quad-Speed Mode.
FS
(input)
tfsh
tfss
tsckh
tsckl
SCLK
(input)
tds
tdh1
MSB
DAC_SDIN
MSB-1
tdh2
tdval
MSB-1
ADC_SDOUT
MSB
Figure 5. TDM Serial Audio Interface Timing
DS646PP2
21
CIRRUS [ CIRRUS LOGIC ]
