Hardware Mode Feature Summary
Default Configuration
Function
Hardware Control
Note
AIN5 Multiplexer
Selects between AIN5A and
AIN5B when ADC3 in Sin-
gle-Ended Mode
“AIN5_MUX” pin 1
see section
5.2.2
AIN6 Multiplexer
Selects between AIN6A and
AIN6B when ADC3 in Sin-
gle-Ended Mode
“AIN6_MUX” pin 2
-
see section
5.2.2
DAC Volume Control/Mute/Invert
All DAC Volume = 0 dB, un-
muted, not inverted
-
ADC Volume Control
DAC Soft Ramp/Zero Cross
ADC Soft Ramp/Zero Cross
DAC Auto-Mute
All ADC Volume = 0 dB
Immediate Change
Immediate Change
Enabled
-
-
-
-
-
-
-
-
-
-
Status Interrupt
N/A
Table 2. Hardware Configurable Settings
5.2
Analog Inputs
5.2.1 Line Level Inputs
AINx+ and AINx- are the line level differential analog inputs internally biased to VQ, approxi-
mately VA/2. Figure 9 on page 28 shows the full-scale analog input levels. The CS42438 also
accommodates single-ended signals on all inputs, AIN1-AIN6. See “ADC Input Filter” on
page 51 for the recommended input filters.
Hardware Mode
AIN Volume Control and ADC Overflow status are not accessible in Hardware Mode. Single-
ended operation is only supported for ADC3. See section 5.2.2 below.
Software Mode
For single-ended operation on ADC1-ADC3 (AIN1 to AIN6), the ADCx_SINGLE bit in the regis-
ter “ADC Control & DAC De-emphasis (address 05h)” on page 45 must be set appropriately (see
Figure 21 on page 51 for required external components).
The gain/attenuation of the signal can be adjusted for each AINx independently through the
“AINX Volume Control (address 11h-16h)” on page 49. The ADC output data is in 2’s comple-
ment binary format. For inputs above positive full scale or below negative full scale, the ADC will
output 7FFFFFH or 800000H, respectively and cause the ADC Overflow bit in the register “Sta-
tus (address 19h) (Read Only)” on page 50 to be set to a ‘1’.
DS646PP2
27
CIRRUS [ CIRRUS LOGIC ]
