5 APPLICATIONS
5.1 Overview
The CS42438 is a highly integrated mixed signal 24-bit audio CODEC comprised of 6 analog-to-digital
converters (ADC), implemented using multi-bit delta-sigma techniques, and 8 digital-to-analog converters
(DAC) also implemented using multi-bit delta-sigma techniques.
Other functions integrated within the CODEC include independent digital volume controls for each DAC,
digital de-emphasis filters for the DAC, digital volume control with gain on each ADC channel, ADC high-
pass filters, and an on-chip voltage reference.
The serial audio interface ports allow up to 8 DAC channels and 8 ADC channels in a Time-Division Mul-
tiplexed (TDM) interface format. The CS42438 features an Auxiliary Port used to accommodate an addi-
tional two channels of PCM data on the ADC_SDOUT data line in the TDM digital interface format. See
“AUX Port Digital Interface Formats” on page 35 for details.
The CS42438 operates in one of three oversampling modes based on the input sample rate. Mode selec-
tion is determined automatically based on the MCLK frequency setting. Single-Speed mode (SSM) sup-
ports input sample rates up to 50 kHz and uses a 128x oversampling ratio. Double-Speed mode (DSM)
supports input sample rates up to 100 kHz and uses an oversampling ratio of 64x. Quad-Speed mode
(QSM) supports input sample rates up to 200 kHz and uses an oversampling ratio of 32x (NOTE: QSM
for the ADC is only supported in the I²S, Left-Justified, Right-Justified interface formats. QSM is not sup-
ported for the ADC). NOTE: QSM is only available in software mode (see section 5.4 on page 33 for de-
tails).
All functions can be configured through software via a serial control port operable in SPI mode or in I²C
mode. A hardware, stand-alone mode is also available, allowing configuration of the CODEC on a more
limited basis. See Table 2 for the default configuration in Hardware Mode.
Figure 1 on page 10 and Figure 2 on page 11 show the recommended connections for the CS42438 in
software and hardware mode, respectively. See section “Register Description” on page 42 for the default
register settings and options in Software Mode.
Hardware Mode Feature Summary
Function
Default Configuration
All ADC’s are enabled
All DAC’s are enabled
Device is powered up
Hardware Control
Note
Power Down ADC
Power Down DAC
Power Down Device
MCLK Frequency Select
-
-
-
-
-
-
Selectable between 256Fs
and 512Fs
“MFREQ” pin 3
see section
5.4
Freeze Control
N/A
-
-
-
-
-
-
AUX Serial Port Interface Format
ADC1/ADC2 High Pass Filter Freeze
Left-Justified
High Pass Filter is always
enabled
ADC3 High Pass Filter Freeze
High Pass Filter can be
enabled/disabled
“ADC3_HPF” pin 4
see section
5.2.3
DAC De-Emphasis
No De-Emphasis applied
Disabled
-
-
-
-
ADC1/ADC2 Single-Ended Mode
ADC3 Single-Ended Mode
Selectable between Differ-
ential and Single-Ended
“ADC_SDOUT/
ADC3_SINGLE” pin 13
see section
5.2.2
Table 2. Hardware Configurable Settings
26
DS646PP2
CIRRUS [ CIRRUS LOGIC ]
