CS42426
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI™ FORMAT
(For CQZ, T = -10 to +70° C; For DQZ, T = -40 to +85° C; VA = 5 V, VD =VLS= 3.3 V; VLC = 1.8 V to 5.25 V;
A
A
Inputs: Logic 0 = DGND, Logic 1 = VLC, C = 30 pF)
L
Parameter
CCLK Clock Frequency
Symbol
fsck
tcsh
tcss
tscl
Min
0
Typ
Max
Units
MHz
µs
-
-
-
-
-
-
-
-
-
-
-
-
6.0
-
CS High Time Between Transmissions
CS Falling to CCLK Edge
CCLK Low Time
1.0
20
66
66
40
15
-
-
ns
-
ns
CCLK High Time
tsch
tdsu
tdh
-
ns
CDIN to CCLK Rising Setup Time
CCLK Rising to DATA Hold Time
CCLK Falling to CDOUT Stable
Rise Time of CDOUT
-
ns
(Note 20)
-
ns
tpd
50
25
25
100
100
ns
tr1
-
ns
Fall Time of CDOUT
tf1
-
ns
Rise Time of CCLK and CDIN
Fall Time of CCLK and CDIN
(Note 21)
(Note 21)
tr2
-
ns
tf2
-
ns
Notes:
20. Data must be held for sufficient time to bridge the transition time of CCLK.
21. For f <1 MHz.
sck
CS
t
t
scl
sch
t
t
csh
css
CCLK
t
t
r2
f2
CDIN
t
dsu
t
dh
t
pd
CDOUT
Figure 4. Control Port Timing - SPI Format
DS604F1
13
CIRRUS [ CIRRUS LOGIC ]
