CS42426
SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMAT
(For CQZ, T = -10 to +70° C; For DQZ, T = -40 to +85° C; VA = 5 V, VD =VLS= 3.3 V; VLC = 1.8 V to 5.25 V;
A
A
Inputs: Logic 0 = DGND, Logic 1 = VLC, C = 30 pF)
L
Parameter
SCL Clock Frequency
Symbol
fscl
Min
-
Max
Unit
kHz
ns
100
RST Rising Edge to Start
tirs
500
4.7
4.0
4.7
4.0
4.7
0
-
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low time
tbuf
-
µs
thdst
tlow
-
µs
-
µs
Clock High Time
thigh
tsust
thdd
tsud
trc
-
µs
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling
SDA Setup time to SCL Rising
Rise Time of SCL and SDA
-
µs
(Note 17)
(Note 18)
-
µs
250
-
-
ns
1
300
µs
Fall Time SCL and SDA
tfc
-
ns
Setup Time for Stop Condition
Acknowledge Delay from SCL Falling
tsusp
tack
4.7
-
-
µs
(Note 19)
ns
Notes:
17. Data must be held for sufficient time to bridge the transition time, t , of SCL.
fc
18. The acknowledge delay is based on MCLK and can limit the maximum transaction speed.
15
256 × Fs
15
128 × Fs
15
64 × Fs
---------------------
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19.
for Single-Speed Mode,
for Double-Speed Mode,
for Quad-Speed Mode
RST
t
irs
Repeated
Start
Stop
Start
Stop
t
t
rd
fd
SDA
SCL
t
t
t
t
t
buf
t
high
hdst
fc
susp
hdst
t
t
t
t
t
t
sust
sud
ack
rc
low
hdd
Figure 3. Control Port Timing - I²C Format
12
DS604F1
CIRRUS [ CIRRUS LOGIC ]
