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CS42416-CQZR 参数 Datasheet PDF下载

CS42416-CQZR图片预览
型号: CS42416-CQZR
PDF下载: 下载PDF文件 查看货源
内容描述: 110分贝192千赫6声道编解码器PLL [110 dB, 192 kHz 6-Ch Codec with PLL]
分类和应用: 解码器编解码器消费电路商用集成电路
文件页数/大小: 73 页 / 1386 K
品牌: CIRRUS [ CIRRUS LOGIC ]
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CS42416  
4.5.4.2 OLM Config #2  
This configuration will support up to 6 channels of DAC data or 6 channels of ADC data and will handle up  
to 20-bit samples at a sampling-frequency of 96 kHz on all channels for both the DAC and ADC. The output  
data stream of the internal and external ADCs is configured to use the ADC_SDOUT output and run at the  
DAC Serial Port sample frequency.  
Register / Bit Settings  
Functional Mode Register (addr = 03h)  
Set DAC_FMx = 00,01,10  
Description  
DAC_LRCK can run at SSM, DSM or QSM independent of ADC_LRCK  
ADC_LRCK can run at SSM, DSM or QSM independent of DAC_LRCK  
Configure ADC_SDOUT to be clocked from the ADC_SP clocks.  
Set ADC_FMx = 00,01,10  
Set ADC_CLK_SEL = 1  
Interface Format Register (addr = 04h)  
Set DIFx bits to proper serial format  
Set ADC_OLx bits = 00,01,10  
Set DAC_OLx bits = 00,01  
Select the digital interface format when not in One-Line Mode  
Select ADC operating mode, see table below for valid combinations  
Select DAC operating mode, see table below for valid combinations  
Misc. Control Register (addr = 05h)  
Set DAC_SP M/S = 1  
Set DAC Serial Port to Master Mode.  
Set ADC Serial Port to Master Mode.  
Set ADC_SP M/S = 1  
Identify external ADC clock source as DAC Serial Port.  
Set EXT ADC SCLK = 1  
DAC Mode  
Not One-Line Mode  
One-Line Mode #1  
DAC_SCLK=128Fs  
One-Line Mode #2  
DAC_SCLK=64Fs  
Not One- DAC_LRCK=SSM/DSM/QSM DAC_LRCK=SSM  
Line Mode ADC_SCLK=64Fs ADC_SCLK=64Fs  
ADC_LRCK=SSM/DSM/QSM ADC_LRCK=SSM/DSM/QSM  
not valid  
not valid  
not valid  
DAC_SCLK=64Fs  
One-Line DAC_LRCK=SSM/DSM  
Mode #1 ADC_SCLK=128Fs  
ADC_LRCK=DAC_LRCK  
DAC_SCLK=128Fs  
DAC_LRCK=SSM  
ADC_SCLK=128Fs  
ADC_LRCK=DAC_LRCK  
ADC Mode  
DAC_SCLK=64Fs  
One-Line DAC_LRCK=SSM  
Mode #2 ADC_SCLK=256Fs  
ADC_LRCK=DAC_LRCK  
not valid  
MCLK  
64Fs,128Fs,  
256Fs  
SCLK_PORT1  
LRCK  
SCLK  
ADC_SCLK  
ADC_LRCK  
ADC_SDOUT  
LRCK_PORT1  
SDIN_PORT1  
ADC Data  
MCLK  
SDOUT1  
SDOUT2  
RMCK  
ADCIN1  
ADCIN2  
CS5361  
64Fs,128Fs  
CS5361  
SCLK_PORT2  
LRCK_PORT2  
DAC_SCLK  
DAC_LRCK  
DAC_SDIN1  
DAC_SDIN2  
SDOUT1_PORT2  
SDOUT2_PORT2  
SDOUT3_PORT2  
DAC_SDIN3  
DIGITAL AUDIO  
PROCESSOR  
CS42416  
Figure 18. OLM Configuration #2  
32  
DS602F1  
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