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CS42416-CQZR 参数 Datasheet PDF下载

CS42416-CQZR图片预览
型号: CS42416-CQZR
PDF下载: 下载PDF文件 查看货源
内容描述: 110分贝192千赫6声道编解码器PLL [110 dB, 192 kHz 6-Ch Codec with PLL]
分类和应用: 解码器编解码器消费电路商用集成电路
文件页数/大小: 73 页 / 1386 K
品牌: CIRRUS [ CIRRUS LOGIC ]
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CS42416  
4.6.2  
I²C Mode  
In I²C mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL.  
There is no CS pin. Pins AD0 and AD1 form the two least-significant bits of the chip address and should  
be connected through a resistor to VLC or DGND as desired. The state of the pins is sensed while the  
CS42416 is being reset.  
The signal timings for a read and write cycle are shown in Figure 22 and Figure 23. A Start condition is  
defined as a falling transition of SDA while the clock is high. A Stop condition is a rising transition while  
the clock is high. All other transitions of SDA occur while the clock is low. The first byte sent to the  
CS42416 after a Start condition consists of a 7-bit chip address field and a R/W bit (high for a read, low  
for a write). The upper 5 bits of the 7-bit address field are fixed at 10011. To communicate with a CS42416,  
the chip address field, which is the first byte sent to the CS42416, should match 10011, followed by the  
settings of the AD1 and AD0. The eighth bit of the address is the R/W bit. If the operation is a write, the  
next byte is the Memory Address Pointer (MAP) which selects the register to be read or written. If the op-  
eration is a read, the contents of the register pointed to by the MAP will be output. Setting the auto-incre-  
ment bit in MAP allows successive reads or writes of consecutive registers. Each byte is separated by an  
acknowledge bit. The ACK bit is output from the CS42416 after each input byte is read and is input to the  
CS42416 from the microcontroller after each transmitted byte.  
26  
27 28  
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19  
24 25  
SCL  
SDA  
DATA +1  
DATA +n  
CHIP ADDRESS (WRITE)  
0 0 1 1 AD1 AD0  
MAP BYTE  
DATA  
1
0
INCR  
6
5
4
3
2
1
0
7
6
1
0
7
6
1
0
7
6
1
0
ACK  
ACK  
ACK  
ACK  
STOP  
START  
Figure 22. Control Port Timing, I²C Write  
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25  
26 27 28  
SCL  
STOP  
CHIP ADDRESS (WRITE)  
AD1 AD0  
MAP BYTE  
CHIP ADDRESS (READ)  
AD1 AD0  
DATA  
DATA +1 DATA + n  
1
0
0
1
1
1
SDA  
INCR  
6
5
4
3
2
1
0
1
0
0
1
1
0
7
0
7
0
7
0
ACK  
ACK  
START  
ACK  
ACK  
NO  
ACK  
START  
STOP  
Figure 23. Control Port Timing, I²C Read  
Since the read operation cannot set the MAP, an aborted write operation is used as a preamble. As shown  
in Figure 23, the write operation is aborted after the acknowledge for the MAP byte by sending a stop con-  
dition. The following pseudocode illustrates an aborted write operation followed by a read operation.  
Send start condition.  
Send 10011xx0 (chip address & write operation).  
Receive acknowledge bit.  
Send MAP byte, auto increment off.  
Receive acknowledge bit.  
Send stop condition, aborting write.  
36  
DS602F1