CS42416
DAC_LRCK
ADC_LRCK
Left Channel
Right Channel
DAC_SCLK
ADC_SCLK
DAC_SDINx
ADC_SDOUT
MSB
+5 +4 +3 +2 +1
LSB
MSB
LSB
+5 +4 +3 +2 +1
-1
-2 -3 -4 -5
-1 -2 -3 -4
I²S Mode, Data Valid on Rising Edge of SCLK
Bits/Sample
SCLK Rate(s)
Notes
Master
Slave
64 Fs
64 Fs
64 Fs
48, 64, 128 Fs
64 Fs
Single-Speed Mode
Double-Speed Mode
Quad-Speed Mode
Single-Speed Mode
Double-Speed Mode
Quad-Speed Mode
16
64 Fs
64, 128, 256 Fs
64 Fs
48, 64, 128 Fs
64 Fs
18 to 24
64 Fs
64 Fs
Figure 12. I²S Serial Audio Formats
DAC_LRCK
ADC_LRCK
Left Channel
Right Channel
DAC_SCLK
ADC_SCLK
DAC_SDINx
ADC_SDOUT
MSB
LSB
MSB
LSB
+5 +4 +3 +2 +1
+5 +4 +3 +2 +1
-1 -2 -3 -4 -5
-1 -2 -3 -4
Left-Justified Mode, Data Valid on Rising Edge of SCLK
Bits/Sample
SCLK Rate(s)
Notes
Master
Slave
64 Fs
64 Fs
64 Fs
32, 48, 64, 128 Fs
32, 64 Fs
Single-Speed Mode
Double-Speed Mode
Quad-Speed Mode
Single-Speed Mode
Double-Speed Mode
Quad-Speed Mode
16
32, 64 Fs
64, 128, 256 Fs
64 Fs
48, 64, 128 Fs
64 Fs
18 to 24
64 Fs
64 Fs
Figure 13. Left-Justified Serial Audio Formats
28
DS602F1
CIRRUS [ CIRRUS LOGIC ]
