CL-PD6710/’22
ISA–to–PC-Card Host Adapters
10. TIMING REGISTERS
The following information about the timing registers is important:
● All timing registers take effect immediately and should only be changed when the FIFO is empty (see the
FIFO Control register on page 60).
● Selection of Timing 0 or Timing 1 register sets is controlled by I/O Window Control, bit 3 and/or bit 7 (see
page 49).
10.1 Setup Timing 0–1
Register Name: Setup Timing 0–1
Index: 3Ah, 3Dh
Register Per: socket
Register Compatibility Type: 365
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Setup Prescalar Select
RW:00
Setup Multiplier Value
RW:000001
There are two separate Setup Timing registers, each with identical fields. These registers are located at
the following indexes:
Index
Setup Timing
3Ah
3Dh
Setup Timing 0
Setup Timing 1
The Setup Timing register for each timing set controls how long a PC Card cycle’s command (that is, -OE,
-WE, -IORD, -IOWR; see page 16) setup will be, in terms of the number of internal clock cycles.
The overall command setup number of clocks S is programmed by selecting a 2-bit prescaling value (bits
7:6 of this register) representing weights of 1, 16, 256, or 8192, and then selecting a multiplier value (bits
5:0) to which that prescalar is multiplied to produce the overall command setup timing length according
to the following formula:
S = (N
× N ) + 1
Equation 10-1
pres
val
The value of S, representing the number of internal clock cycles for command setup, is then multiplied by
the internal clock’s period to determine the command setup time (see Section 15.3.6 for further discussion).
Bits 5:0 — Setup Multiplier Value
This field indicates an integer value N from 0 to 63; it is combined with a prescalar value (bits
val
7:6) to control the length of setup time before a command becomes active.
Bits 7:6 — Setup Prescalar Select
00
01
10
11
N
N
N
N
= 1
pres
pres
pres
pres
= 16
= 256
= 8192
This field chooses one of four prescalar values N
that are combined with the value of the Setup
pres
Multiplier Value (bits 5:0) to control the length of setup time before a command becomes active.
72
May 1997
TIMING REGISTERS
PRELIMINARY DATA SHEET v3.1
CIRRUS [ CIRRUS LOGIC ]
