CL-PD6710/’22
ISA–to–PC-Card Host Adapters
10.3 Recovery Timing 0–1
Register Name: Recovery Timing 0–1
Index: 3Ch, 3Fh
Register Per: socket
Register Compatibility Type: 365
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Recovery Prescalar Select
RW:00
Recovery Multiplier Value
RW:000011
There are two separate Recover Timing registers, each with identical fields. These registers are located
at the following indexes:
Index
Recovery Timing
3Ch
3Fh
Recovery Timing 0
Recovery Timing 1
The Recovery Timing register for each timing set controls how long a PC Card cycle’s command (that is,
-OE, -WE, -IORD, -IOWR; see page 16) recovery will be, in terms of the number of internal clock cycles.
The overall command recovery timing length R is programmed by selecting a 2-bit prescaling value (bits
7:6 of this register) representing weights of 1, 16, 256, or 8192, and then selecting a multiplier value (bits
5:0) to which that prescalar is multiplied to produce the overall command recovery timing length according
to the following formula:
R = (N
× N ) + 1
Equation 10-3
pres
val
The value of R, representing the number of internal clock cycles for command recovery, is then multiplied
by the internal clock’s period to determine the command recovery time (see Section 15.3.6 for further dis-
cussion).
Bits 5:0 — Recovery Multiplier Value
This field indicates an integer value N from 0 to 63; it is combined with a prescalar value (bits
val
7:6) to control the length of recovery time after a command is active.
Bits 7:6 — Recovery Prescalar Select
00
01
10
11
N
N
N
N
= 1
pres
pres
pres
pres
= 16
= 256
= 8192
This field chooses one of four prescalar values N
that are combined with the value of the Re-
pres
covery Multiplier Value (bits 5:0) to control the length of recovery time after a command is active.
74
May 1997
TIMING REGISTERS
PRELIMINARY DATA SHEET v3.1
CIRRUS [ CIRRUS LOGIC ]
