CL-PD6710/’22
ISA–to–PC-Card Host Adapters
9. EXTENSION REGISTERS
9.1 Misc Control 1
Register Name: Misc Control 1
Index: 16h
Register Per: socket
Register Compatibility Type: ext.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
5 V Detect
(CL-PD6710)
Pulse
Management
Interrupt
Speaker
Enable
Pulse System
IRQ
Inpack Enable
RW:0
Scratchpad Bits
V
3.3V
CC
a
Reserved
(CL-PD6722)
RW:00
RW:0
RW:0
RW:0
RW:0
R:X W:0
a
On some versions of the CL-PD6722, this bit can be used to read levels of the A_GPSTB and B_GPSTB pins. Contact Cirrus
Logic for more information.
Bit 0 — 5 V Detect (CL-PD6710 only)
0
1
3.3 V card detected.
Old or 5 V card detected.
This bit is connected to pins VS1 and VS2. Cards that will only operate at 3.3 V will drive this bit
to ‘0’.
Bit 1 — VCC 3.3V
0
-VCC_5 activated when card power is to be applied.
-VCC_3 activated when card power is to be applied.
1
This bit determines which output pin is to be used to enable V power to the socket when card
CC
power is to be applied; it is used in conjunction with bits 5:4 of the Power Control register (see
page 40).
Bit 2 — Pulse Management Interrupt
0
Card status change management interrupts are passed to the appropriate IRQ[XX] or -INTR pin as
level-sensitive.
1
When a card status change management interrupt occurs, the appropriate IRQ[XX] or -INTR pin is
driven with the pulse train shown in Figure 9-1 and allows for interrupt sharing.
This bit selects Level or Pulse mode operation of the IRQ[XX] or -INTR pin being used for card
status change management interrupts (see page 14). Note that a clock must be present on the
incoming CLK for pulsed interrupts to work.
58
May 1997
EXTENSION REGISTERS
PRELIMINARY DATA SHEET v3.1
CIRRUS [ CIRRUS LOGIC ]
