欢迎访问ic37.com |
会员登录 免费注册
发布采购

CL-PD6710-VC-A 参数 Datasheet PDF下载

CL-PD6710-VC-A图片预览
型号: CL-PD6710-VC-A
PDF下载: 下载PDF文件 查看货源
内容描述: [PCMCIA Bus Controller, MOS, PQFP144, VQFP-144]
分类和应用: PC
文件页数/大小: 128 页 / 1552 K
品牌: CIRRUS [ CIRRUS LOGIC ]
 浏览型号CL-PD6710-VC-A的Datasheet PDF文件第51页浏览型号CL-PD6710-VC-A的Datasheet PDF文件第52页浏览型号CL-PD6710-VC-A的Datasheet PDF文件第53页浏览型号CL-PD6710-VC-A的Datasheet PDF文件第54页浏览型号CL-PD6710-VC-A的Datasheet PDF文件第56页浏览型号CL-PD6710-VC-A的Datasheet PDF文件第57页浏览型号CL-PD6710-VC-A的Datasheet PDF文件第58页浏览型号CL-PD6710-VC-A的Datasheet PDF文件第59页  
CL-PD6710/’22  
ISA–to–PC-Card Host Adapters  
Bits 7:0 — End Address 19:12  
This register contains the least-significant byte of the address that specifies where in the memory  
space the corresponding memory map will end. Memory accesses that are equal or below this  
address and equal or above the corresponding System Memory Map Start Address will be  
mapped into the memory space of the corresponding PC Card.  
The most-significant four bits are located in the System Memory Map 0–4 End Address High  
register (see Section 8.4).  
8.4 System Memory Map 0–4 End Address High  
Register Name: System Memory Map 0–4 End Address High  
Index: 13h, 1Bh, 23h, 2Bh, 33h  
Register Per: socket  
Register Compatibility Type: 365  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Card Timer Select  
RW:00  
Scratchpad Bits  
End Address 23:20  
RW:0000  
RW:00  
There are five separate System Memory Map End Address High registers, each with identical fields.  
These registers are located at the following indexes:  
Index  
System Memory Map End Address High  
13h  
1Bh  
23h  
2Bh  
33h  
System Memory Map 0 End Address High  
System Memory Map 1 End Address High  
System Memory Map 2 End Address High  
System Memory Map 3 End Address High  
System Memory Map 4 End Address High  
Bits 3:0 — End Address 23:20  
This field contains the most-significant four bits of the End Address. See the description of the End  
Address field associated with bits 7:0 of the System Memory Map 0–4 End Address Low regis-  
ter (see page 54).  
Bits 7:6 — Card Timer Select  
00  
01  
10  
11  
Selects Timer Set 0.  
Selects Timer Set 1.  
Selects Timer Set 1.  
Selects Timer Set 1.  
This field selects the Timeset registers used to control socket timing for card accesses in this  
window address range. Timeset 0 and 1 reset to values compatible with PC Card standards. The  
mapping of bits 7:6 to Timeset 0 and 1, as shown in the preceding table, is done for software  
compatibility with older ISA bus-based PCMCIA host adapters that use ISA bus wait states instead  
of Timeset registers (see page 72).  
May 1997  
55  
PRELIMINARY DATA SHEET v3.1  
MEMORY WINDOW MAPPING REGISTERS