CL-PD6710/’22
ISA–to–PC-Card Host Adapters
9.2 FIFO Control
Register Name: FIFO Control
Index: 17h
Register Per: socket
Register Compatibility Type: ext.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Empty Write
FIFO
a
Scratchpad Bits
RW:0000000
RW
a
Because a write will flush the FIFO, these scratchpad bits should be used only when card activity is guaranteed not to occur.
Bit 7 — Empty Write FIFO
Value
I/O Read
I/O Write
0
1
FIFO not empty
FIFO empty
No operation occurs; default on reset
Flush the FIFO
This bit controls FIFO operation and reports FIFO status. When this bit is written to ‘1’, all data in
the FIFO is lost. During read operations when this bit is ‘1’, the FIFO is empty. During read oper-
ations when this bit is ‘0’, data is still in the FIFO. This bit is used to ensure the FIFO is empty be-
fore changing timing registers.
FIFO contents will be lost whenever any of the following occur:
● PWRGOOD pin (see page 13) is ‘0’.
● The card is removed.
● V
Power bit (see page 41) is programmed to ‘0’.
CC
60
May 1997
EXTENSION REGISTERS
PRELIMINARY DATA SHEET v3.1
CIRRUS [ CIRRUS LOGIC ]
