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CL-PD6710-VC-A 参数 Datasheet PDF下载

CL-PD6710-VC-A图片预览
型号: CL-PD6710-VC-A
PDF下载: 下载PDF文件 查看货源
内容描述: [PCMCIA Bus Controller, MOS, PQFP144, VQFP-144]
分类和应用: PC
文件页数/大小: 128 页 / 1552 K
品牌: CIRRUS [ CIRRUS LOGIC ]
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CL-PD6710/’22  
ISA–to–PC-Card Host Adapters  
9.3 Misc Control 2  
Register Name: Misc Control 2  
Index: 1Eh  
Register Per: chip  
Register Compatibility Type: ext.  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Low-Power  
Dynamic  
Mode  
Bypass  
Frequency  
Synthesizer  
IRQ15 Is RI DMA System Three-State  
Drive LED  
Enable  
5V Core  
RW:0  
Suspend  
RW:0  
Out  
(CL-PD6722)  
RW:0  
Bit 7  
RW:0  
RW:0  
RW:0  
RW:1  
RW:0  
Bit 0 — Bypass Frequency Synthesizer  
0
1
Normal operation, internal clock = CLK input frequency x 7/4.  
Internal clock = CLK input frequency (see page 15).  
This bit determines internal time base.  
Bit 1 — Low-Power Dynamic Mode  
0
1
Clock runs always.  
Normal operation, stop clock when possible.  
This bit determines whether Low-Power Dynamic mode is enabled. For maximum operational  
power savings, keep this bit set to ‘1’.  
Bit 2 — Suspend  
0
Normal operation.  
1
Stop Frequency Synthesizer, enable all Low-Power modes and disable socket access.  
This bit enables Suspend mode. After entering Suspend, AEN should be pulled high for lowest  
power consumption. When this bit is high and AEN is high, all ISA bus interface inputs are turned  
off. In 82386SL systems when the processor is in Suspend mode, the ISA bus interface signals  
float; this feature will prevent high current flow in the CL-PD67XX inputs.  
Bit 3 — 5V Core  
0
Normal operation: use when CORE_VDD pin is connected to 3.3 volts.  
1
Selects input thresholds for use when 5.0 volts is connected to the CL-PD67XX CORE_VDD pins.  
This bit selects input threshold circuits for use when 3.3 or 5.0 volts is connected to the  
CL-PD67XX CORE_VDD pins.This bit must be set to ‘0’ when the CORE_VDD pins are connect-  
ed to 3.3 volts to preserve TTL-compatible input thresholds to the card socket.  
Bit 4 — Drive LED Enable  
0
IRQ12 operates normally.  
1
IRQ12 becomes an open-drain output suitable for driving an LED (driven whenever the card -SPKR  
output is turned on, and the corresponding Speaker Is LED input bit (see page 64) is set).  
NOTE:This bit should be set to ‘0’ if in Memory Card Interface mode.  
This bit determines whether -SPKR is used to drive an LED on the IRQ12 (see page 14) for disk  
drives.  
May 1997  
61  
PRELIMINARY DATA SHEET v3.1  
EXTENSION REGISTERS