CL-PD6710/’22
ISA–to–PC-Card Host Adapters
7.6 Card I/O Map 0–1 Offset Address Low
Register Name: Card I/O Map 0–1 Offset Address Low
Index: 36h, 38h
Register Per: socket
Register Compatibility Type: ext.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
a
Offset Address 7:1
RW:0000000
0
RW:0
a
This bit must be programmed to ‘0’.
There are two separate Card I/O Map Offset Address Low registers, each with identical fields.These reg-
isters are located at the following indexes:
Index
Card I/O Map Offset Address Low
36h
38h
Card I/O Map 0 Offset Address Low
Card I/O Map 1 Offset Address Low
Bits 7:1 — Offset Address 7:1
This register contains the least-significant byte of the quantity that will be added to the host I/O
address; this will determine the PC Card I/O map location where the I/O access will occur.
The most-significant byte is located in the Card I/O Map 0–1 Offset Address High register (see
page 52).
7.7 Card I/O Map 0–1 Offset Address High
Register Name: Card I/O Map 0–1 Offset Address High
Index: 37h, 39h
Register Per: socket
Register Compatibility Type: ext.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Offset Address 15:8
RW:00000000
There are two separate Card I/O Map Offset Address High registers, each with identical fields.These reg-
isters are located at the following indexes:
Index
Card I/O Map Offset Address High
37h
39h
Card I/O Map 0 Offset Address High
Card I/O Map 1 Offset Address High
Bits 15:8 — Offset Address 15:8
This register contains the most-significant byte of the Offset Address. See the description of the
End Address field associated with bits 7:1 of the Card I/O Map 0–1 Offset Address Low register
(see page 52).
52
May 1997
I/O WINDOW MAPPING REGISTERS
PRELIMINARY DATA SHEET v3.1
CIRRUS [ CIRRUS LOGIC ]
