CL-PD6710/’22
ISA–to–PC-Card Host Adapters
Bit Naming Conventions
4. REGISTER DESCRIPTION
CONVENTIONS
The following keywords are used within bit and
field names:
Register Headings
Keyword
Description
The description of each register starts with a
header containing the following information:
Indicates that the function described in
the rest of the bit name is active when
the bit is ‘1’.
Enable
Header Field Description
Indicates that the function described in
the rest of the bit name is active when
the bit is ‘0’.
Disable
Mode
Register Name Indicates the register name.
The Index value through which an inter-
nal register in an indexed register set is
accessed.
Indicates that the function of the bit
alters the interpretation of the values in
other registers.
a
Index
Indicates whether the register affects
both sockets, marked chip, or an individ-
ual socket, marked socket. If socket is
indicated, there are two registers being
described, each with a separate Index
Indicates a bit or field that is read from a
pin.
Input
Register Per
Indicates a bit or field that is driven to a
pin.
Output
a
value (one for each socket, A and B).
Indicates that the bit or field selects
between multiple alternatives. Fields
that contain Select in their names have
an indirect mapping between the value
of the field and the effect.
Register
Compatibility
Type
Indicates whether the register is
82365SL-compatible, marked 365 or a
register extension, marked ext.
Select
a
When the register is socket-specific, the Index value given
in the register heading is for Socket A only. For the Socket
B register on the CL-PD6722, add 40h to the Index value of
the Socket A register.
Indicates one of two types of bits: either
read-only bits used by the CL-PD67XX
to report information to the system, or
bits set by the CL-PD67XX in response
to an event, and can also be cleared by
the system. The system cannot directly
cause a Status bit to become ‘1’.
Status
Value
Special Function Bits
Following is a description of bits with special func-
tions:
Indicates that the bit or field value is
used as a number.
Bit Type
Description
Read/Write Convention
These bits are Reserved and should not
be changed.
Reserved
Bit Access
Description
These bits have no function on the
CL-PD67XX, but are included for com-
patibility with the 82365SL register set.
Bit is read/write and resets to value n
when PWRGOOD is cycled.
Compatibility
Bit
RW:n
Bit is read-only and setting is deter-
mined by conditions noted. Set this bit
to ‘0’, or echo back value read.
These read-only bits are forced to either
‘0’ or ‘1’ at reset and cannot be
changed.
R
0 or 1
Bit is read-only and resets to value n
when PWRGOOD is cycled. Set this bit
to ‘0’, or echo back value read.
These read/write bits are available for
use as bits of memory.
R:n
Scratchpad Bit
Bit is read/write and resets to value n
when PWRGOOD is cycled. Set this bit
to value m only.
R:n W:m
32
May 1997
REGISTER DESCRIPTION CONVENTIONS
PRELIMINARY DATA SHEET v3.1
CIRRUS [ CIRRUS LOGIC ]
