CL-PD6710/’22
ISA–to–PC-Card Host Adapters
3.1.14 DMA Mode Operation for the
CL-PD6722
CL-PD67XX can be programmed through use of its
Data Mask registers to disable bit 7 on I/O reads at
addresses 3F7h and 377h.This is done by program-
ming up I/O windows to these addresses as part of
the task of configuring a socket for ATA drive support
(see page 65). Alternately, all bits except bit 7 can
also be disabled to allow the opposite case.
A slave mode Direct Memory Access (DMA) feature
exists in the CL-PD6722. To use DMA mode, the
Interrupt and General Control register, bit 5 must
be set to‘1’to operate the PC Card in I/O Card Inter-
face mode. PC Card interface DMA handshake sig-
nal options must also be selected. Refer to the
description of the Extension Control 1 register on
page 66 as well as Chapter 14.
3.2 Host Access to Registers
The CL-PD67XX registers are accessed through an
8-bit indexing mechanism. An index register
scheme allows a large number of internal registers
to be accessed by the CPU using only two I/O
addresses.
3.1.15 Selective Data Drive for I/O Windows
The CL-PD67XX can be programmed to drive only
some of the ISA bus data pins on reads from I/O win-
dows. This reduces data contention for I/O
addresses that include more than one peripheral. In
the standard IBM PC AT, I/O map, floppy disk, and
hard disk share address 3F7h. The floppy disk
drives ISA-data-bus bit 7 on a read from 3F7h, and
the hard disk drives bits 6:0. To allow both floppy
disk controllers on the motherboard and hard disks
on the PC Card bus (or vice versa) to coexist, the
The Index register (see Chapter 5) is used to spec-
ify which of the internal registers the CPU will
access next.The value in the Index register is called
the Register Index. This number specifies a unique
internal register. The Data register is used by the
CPU to read and write the internal register specified
by the Index register.
Internal Registers
FFh
FEh
•
•
•
Register
Indexes
02h
01h
00h
High Byte
Data
Low Byte
Index
3E0h
3E1h
I/O Addresses
Figure 3-4. Indexed 8-Bit Register Structure
30
May 1997
INTRODUCTION
PRELIMINARY DATA SHEET v3.1
CIRRUS [ CIRRUS LOGIC ]
