CL-PD6710/’22
ISA–to–PC-Card Host Adapters
5. OPERATION REGISTERS
The CL-PD67XX internal registers are accessed through a pair of Operation registers — an Index register
and a Data register.The Index register is accessed at address 03E0h, and the Data register is accessed
at 03E1h.
5.1 Index
Register Name: Index
Index: n/a
Register Per: chip
Register Compatibility Type: 365
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Device Index Socket Index
Register Index
RW:0
RW:0
RW:000000
The Data register is accessed at 03E1h.
Bits 5:0 — Register Index
These bits determine which of the 64 possible socket-specific registers will be accessed when the
Data register is next accessed by the processor. Note that some values of the Register Index field
are reserved (see Table 5-1).
Bit 6 — Socket Index
This bit determines which set of socket-specific registers is currently selected. When this bit is ‘0’,
a Socket A register is selected. When this bit is ‘1’, a Socket B register is selected. Note that the
CL-PD6710 supports one socket, and the CL-PD6722 supports two sockets.
Bit 7 — Device Index
In systems where two CL-PD67XXs are used, this bit differentiates between them.
The Index register value determines which internal register should be accessed (read or written) in
response to each CPU access of the Data register. Each of the possible PC Card sockets is allocated 64
of the 256 locations in the internal register index space.
FFh
Socket D Registers
Possible with two CL-PD67XXs
Socket C Registers
80h
7Fh
Socket B Registers
40h
3Fh
Socket A Registers
00h
Figure 5-1. Device/Socket/Register Index Space
When viewed as a 8-bit value, the contents of the Index register completely specify a single internal-reg-
ister byte. For example, when the value of this register is in the range 00h–3Fh, a Socket A register is
selected (Socket Index bit is ‘0’), and when the value of this register is in the range 40h–7Fh, a Socket B
register is selected (Socket Index bit is ‘1’). This register only reads back for Device 0. Device 1 will read
back only the upper data byte when 16-bit reads occur at 3E0h.
May 1997
33
PRELIMINARY DATA SHEET v3.1
OPERATION REGISTERS
CIRRUS [ CIRRUS LOGIC ]
