Application Information: continued
The input filter inductor may not be required because bulk 7) The MOSFET gate traces to the IC must be as short,
filter and bypass capacitors, as well as other loads located
on the board will tend to reduce regulator di/dt effects on
straight, and wide as possible.
the circuit board and input power supply. Placement of the 8) Use fewer, but larger output capacitors, keep the capaci-
power component to minimize routing distance will also
help to reduce emissions.
tors clustered, and use multiple layer traces with heavy
copper to keep the parasitic resistance low.
9) Place the switching MOSFET as close to the +5V input
capacitors as possible.
Layout Guidelines
10) Place the output capacitors as close to the load as
possible.
When laying out the CPU buck regulator on a printed cir-
cuit board, the following checklist should be used to
ensure proper operation of the CS51311.
11) Place the VFB,VOUT filter resistors (510Ω) in series with
the VFB and VOUT pins as close as possible to the pins.
1) Rapid changes in voltage across parasitic capacitors and
abrupt changes in current in parasitic inductors are major
concerns for a good layout.
12) Place the COFF and COMP capacitor as close as possible
to the COFF and COMP pins.
13) Place the current limit filter capacitor between the VFB
and VOUT pins, as close as possible to the pins.
2) Keep high currents out of sensitive ground connections.
3) Avoid ground loops as they pick up noise. Use star or
single point grounding.
14) Connect the filter components of the following pins:
VFB, VOUT, COFF, and COMP to the Gnd pin with a single
trace, and connect this local Gnd trace to the output capaci-
tor Gnd.
4) For high power buck regulators on double-sided PCBs a
single ground plane (usually the bottom) is recommended.
15) The “Droop” Resistor (embedded PCB trace) has to be
wide enough to carry the full load current.
5) Even though double sided PCBs are usually sufficient
for a good layout, four-layer PCBs are the optimum
approach to reducing susceptibility to noise. Use the two
internal layers as the Power and Gnd planes, the top layer
for the power connections, and component vias, and the
bottom layer for noise sensitive traces.
16) Place the VCC bypass capacitor as close as possible to
the IC.
6) Keep the inductor switching node small by placing the
output inductor, switching and synchronous FETs close
together.
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