Application Information: continued
1.26 mil to 1.48 mil. Therefore the error due to sheet resis-
Therefore, the regulator output is pre-positioned at 25mV
above the nominal output voltage before a load turn-on.
The total voltage drop due to a load step is ∆V-25mV and
the deviation from the nominal output voltage is 25mV
smaller than it would be if there was no droop resistor.
Similarly at full load the regulator output is pre-positioned
at 25mV below the nominal voltage before a load turn-off.
the total voltage increase due to a load turn-off is ∆V-25mV
and the deviation from the nominal output voltage is
25mV smaller than it would be if there was no droop resis-
tor. This is because the output capacitors are pre-charged
to a value that is either 25mV above the nominal output
voltage before a load turn-on or, 25mV below the nominal
output voltage before a load turn-off .
tivity is:
1.48 - 1.26
1.37
= ±8%.
2) Mismatch due to L/W
The variation in L/W is governed by variations due to the
PCB manufacturing process. The error due to L/W mis-
match is typically 1%.
3) Thermal Considerations
Due to I2 × R power losses the surface temperature of the
droop resistor will increase causing the resistance to
increase. Also, the ambient temperature variation will con-
tribute to the increase of the resistance, according to the
formula:
Obviously, the larger the voltage drop across the droop
resistor (the larger the resistance), the worse the DC and
load regulation, but the better the AC transient response.
R = R20 [1+ α20(Τ−20)],
where
Current Limit
The current limit setpoint has to be higher than the normal
full load current. Attention has to be paid to the current
rating of the external power components as these are the
first to fail during an overload condition. The MOSFET
continuous and pulsed drain current rating at a given case
temperature has to be accounted for when setting the cur-
rent limit trip point.
Temperature curves on MOSFET manufacturers’ data
sheets allow the designer to determine the MOSFET drain
current at a particular VGS and TJ (junction temperature).
This, in turn, will assist the designer to set a proper current
limit, without causing device breakdown during an over-
load condition.
Let’s assume the full CPU load is 16A. The internal current
sense comparator current limit voltage limits are: 77mV <
VTH < 101mV. Also, there is a 21% total variation in RSENSE
as discussed in the previous section.
We compute the value of the current sensing element
(embedded PCB trace) for the minimum current limit set-
point:
R20 = resistance at 20˚C;
0.00393
α =
;
˚C
T= operating temperature;
R = desired droop resistor value.
For temperature T = 50˚C, the % R change = 12%.
Droop Resistor Tolerance
Tolerance due to sheet resistivity variation
Tolerance due to L/W error
Tolerance due to temperature variation
Total tolerance for droop resistor
In order to determine the droop resistor value the nominal
voltage drop across it at full load has to be calculated. This
voltage drop has to be such that the output voltage at full
load is above the minimum DC tolerance spec:
±8%
1%
12%
21%
VDAC(MIN)-VDC(MIN)
VDROOP(TYP)
=
.
RSENSE(MIN) = RSENSE(TYP) × 0.79,
1+RDROOP(TOLERANCE)
Example: for a 450MHz Pentium ®II, the DC accuracy spec
is 1.93 < VCC(CORE) < 2.07V, and the AC accuracy spec is
1.9V < VCC(CORE) < 2.1V. The CS51311 DAC output voltage
is +2.001V < VDAC < +2.049V. In order not to exceed the
DC accuracy spec, the voltage drop developed across the
resistor must be calculated as follows:
RSENSE(MAX) = RSENSE(TYP) × 1.21,
VTH(MIN)
77mV
16A
RSENSE(MAX)
We select,
=
=
= 4.8mΩ.
ICL(MIN)
[VDAC(MIN)-VDC (MIN)
]
VDROOP(TYP)
=
=
RSENSE(TYP) = 3.3mΩ.
1+RDROOP(TOLERANCE)
We calculate the range of load currents that will cause the
internal current sense comparator to detect an overload
condition.
+2.001V-1.93V
= 71mV.
1.21
Nominal Current Limit Setpoint
From the overcurrent detection data in the electrical char-
acteristics table:
With the CS51311 DAC accuracy being 1%, the internal
error amplifier’s reference voltage is trimmed so that the
output voltage will be 25mV high at no load. With no load,
there is no DC drop across the resistor, producing an out-
put voltage tracking the error amplifier output voltage,
including the offset. When the full load current is deliv-
ered, a drop of -50mV is developed across the resistor.
VTH(TYP) = 86mV,
16
CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
