Application Information: continued
Step 9: Slope Compensation
Characteristics section);
SW = switching frequency.
F
Voltage regulators for today’s advanced processors are
expected to meet very stringent load transient require-
ments. One of the key factors in achieving tight dynamic
voltage regulation is low ESR at the CPU input supply
pins. Low ESR at the regulator output results in low output
voltage ripple. The consequence is, however, that there’s
very little voltage ramp at the control IC feedback pin (VFB
and regulator sensitivity to noise and loop instability are
two undesirable effects that can surface. The performance
of the CS51311-based CPU VCC(CORE) regulator is
The total power dissipation in the synchronous (lower)
MOSFET can then be calculated as:
PLFET(TOTAL) = PRMSL + PSWL
,
where
)
PLFET(TOTAL) = Synchronous (lower) FET total losses;
PRMSL = Switch Conduction Losses;
PSWL = Switching losses.
Once the total power dissipation in the synchronous FET is
known the maximum FET switch junction temperature can
be calculated:
improved when a fixed amount of slope compensation is
added to the output of the PWM Error Amplifier (COMP
pin) during the regulator Off-Time. Referring to Figure 11,
the amount of voltage ramp at the COMP pin is dependent
on the gate voltage of the lower (synchronous) FET and the
value of resistor divider formed by R1and R2.
TJ = TA + [PLFET(TOTAL) × RθJA],
where
TJ = MOSFET junction temperature;
TA = ambient temperature;
-t
R2
R1 + R2
VSLOPECOMP = VGATE(L)
×
× (1 − eτ ),
(
)
PLFET(TOTAL) = total synchronous (lower) FET losses;
R
θJA = lower FET junction-to-ambient thermal resistance.
where
Step 8: Control IC Power Dissipation
VSLOPECOMP = amount of slope added;
VGATE(L) = lower MOSFET gate voltage;
R1, R2 = voltage divider resistors;
t = tOFF (switch off-time);
τ = RC constant determined by C1 and the parallel com-
bination of R1, R2 (Figure 11), neglecting the low driver
output impedance
The power dissipation of the IC varies with the MOSFETs
used, VCC, and the CS51311 operating frequency. The aver-
age MOSFET gate charge current typically dominates the
control IC power dissipation.
The IC power dissipation is determined by the formula:
The artificial voltage ramp created by the slope compensa-
tion scheme results in improved control loop stability pro-
vided that the RC filter time constant is smaller than the
off-time cycle duration (time during which the lower MOS-
FET is conducting).
PCONTROLIC = ICCVCC + PGATE(H) + PGATE(L)
,
where
PCONTROLIC = control IC power dissipation;
ICC = IC quiescent supply current;
VCC = IC supply voltage;
PGATE(H) = upper MOSFET gate driver (IC) losses;
PGATE(L) = lower MOSFET gate driver (IC) losses.
Step 10: Selection of Current Limit Filter Components
The current limit filter is implemented by a 0.1µF ceramic
capacitor across and two 510Ω resistors in series with the
VFB and VOUT current limit comparator input pins. They
provide a time constant τ = RC = 100µs, which enables the
circuit to filter out noise and be immune to false triggering,
caused by sudden and fast load changes. These load tran-
sients can have slew rates as high as 20A/µs.
The upper (switching) MOSFET gate driver (IC) losses are:
PGATE(H) = QGATE(H) × FSW × VGATE(H),
where
PGATE(H) = upper MOSFET gate driver (IC) losses;
QGATE(H) = total upper MOSFET gate charge;
FSW = switching frequency;
VGATE(H) = upper MOSFET gate voltage.
The lower (synchronous) MOSFET gate driver (IC) losses
are:
“Droop” Resistor for Adaptive Voltage Positioning
and Current Limit
Adaptive voltage positioning is used to help keep the out-
put voltage within specification during load transients. To
implement adaptive voltage positioning a “Droop
PGATE(L) = QGATE(L) × FSW × VGATE(L),
Resistor” must be connected between the output inductor
and output capacitors and load. This resistor carries the
full load current and should be chosen so that both DC and
AC tolerance limits are met. An embedded PC trace resis-
tor has the distinct advantage of near zero cost implemen-
tation. However, this droop resistor can vary due to three
reasons: 1) the sheet resistivity variation caused by varia-
tion in the thickness of the PCB layer; 2) the mismatch of
L/W; and 3) temperature variation.
where
PGATE(L) = lower MOSFET gate driver (IC) losses;
QGATE(L) = total lower MOSFET gate charge;
FSW = switching frequency;
VGATE(L) = lower MOSFET gate voltage.
The junction temperature of the control IC is primarily a
function of the PCB layout, since most of the heat is
removed through the traces connected to the pins of the IC.
1) Sheet Resistivity
For one ounce copper, the thickness variation is typically
15
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