CAT5259
Figure 2. Write Cycle Timing
SCL
SDA
8TH BIT
BYTE n
ACK
t
WR
STOP
CONDITION
START
CONDITION
ADDRESS
Figure 3. Start/Stop Condition
SDA
SCL
START CONDITION
STOP CONDITION
Figure 4. Acknowledge Condition
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
Figure 5. Slave Address Bits
CAT5259
0
1
0
1
A3 A2 A1 A0
*
A0, A1, A2 and A3 correspond to pin A0, A1, A2 and A3 of the device.
** A0, A1, A2 and A3 must compare to its corresponding hard wired input pins.
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
7
Doc. No. MD-2000 Rev. H