CAT5259
POWER UP TIMING(1)(2)
Symbol Parameter
Max
1
Units
ms
tPUR
tPUW
Power-up to Read Operation
Power-up to Write Operation
1
ms
XDCP TIMING
Symbol Parameter
Min
5
Max
10
Units
µs
tWRPO
tWRL
WRITE CYCLE LIMITS (3)
Wiper Response Time After Power Supply Stable
Wiper Response Time After Instruction Issued
5
10
µs
Symbol
Parameter
Max
Units
tWR
Write Cycle Time
5
ms
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Reference Test Method
Min
Max
Units
Cycles/Byte
Years
V
(4)
NEND
Endurance
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
1,000,000
100
(4)
TDR
Data Retention
ESD Susceptibility
Latch-Up
(4)
VZAP
2000
(4)
ILTH
100
mA
Figure 1. Bus Timing
t
t
t
R
F
HIGH
t
t
LOW
LOW
SCL
t
t
HD:DAT
SU:STA
t
t
t
HD:STA
SU:DAT
SU:STO
SDA IN
t
BUF
t
t
DH
AA
SDA OUT
Notes:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) tPUR and tPUW are delays required from the time VCC is stable until the specified operation can be initiated.
(3) The write cycle is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write
cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address.
(4) This parameter is tested initially and after a design or process change that affects the parameter.
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
5
Doc. No. MD-2000 Rev. H
CATALYST [ CATALYST SEMICONDUCTOR ]
