CAT25080, CAT25160
Write Protection
Write Status Register
¯¯¯
The Write Protect (WP) pin can be used to protect the
Block Protect bits BP0 and BP1 against being
The Status Register is written by sending a WRSR
instruction according to timing shown in Figure 6. Only
bits 2, 3 and 7 can be written using the WRSR
command.
¯¯¯
inadvertently altered. When WP is low and the WPEN
bit is set to “1”, write operations to the Status Register
are inhibited. WP going low while CS is still low will
¯¯¯
¯¯
interrupt a write to the status register. If the internal
¯¯¯
write cycle has already been initiated, WP going low will
have no effect on any write operation to the Status
¯¯¯
Register. The WP pin function is blocked when the
¯¯¯
WPEN bit is set to “0”. The WP input timing is shown in
Figure 7.
Figure 6. WRSR Timing
CS
0
1
2
3
4
5
6
7
1
8
9
6
10
5
11
4
12
13
2
14
1
15
0
SCK
OPCODE
DATA IN
SI
0
0
0
0
0
0
0
7
3
MSB
HIGH IMPEDANCE
SO
Note: Dashed Line = mode (1, 1) - - - - - -
¯¯¯
Figure 7. WP Timing
t
t
WPH
WPS
CS
SCK
WP
WP
Note: Dashed Line = mode (1, 1) - - - - - -
Doc. No. 1122 Rev. A
8
© 2006 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CATALYST [ CATALYST SEMICONDUCTOR ]
