CAT25080, CAT25160
PIN DESCRIPTION
FUNCTIONAL DESCRIPTION
SI: The serial data input pin accepts op-codes,
addresses and data. In SPI modes (0,0) and (1,1)
input data is latched on the rising edge of the SCK
clock input.
The CAT25080/160 devices support the Serial Periphe–
ral Interface (SPI) bus protocol, modes (0,0) and (1,1).
The device contains an 8-bit instruction register. The
instruction set and associated op-codes are listed in
Table 1.
SO: The serial data output pin is used to transfer data
out of the device. In SPI modes (0,0) and (1,1) data is
shifted out on the falling edge of the SCK clock.
Reading data stored in the CAT25080/160 is accom–
plished by simply providing the READ command and an
address. Writing to the CAT25080/160, in addition to a
WRITE command, address and data, also requires
enabling the device for writing by first setting certain bits
in a Status Register, as will be explained later.
SCK: The serial clock input pin accepts the clock
provided by the host and used for synchronizing
communication between host and CAT25080/160.
¯¯
CS: The chip select input pin is used to enable/disable
¯¯
the CAT25080/160. When CS is high, the SO output is
¯¯
After a high to low transition on the CS input pin, the
tri-stated (high impedance) and the device is in
Standby Mode (unless an internal write operation is in
progress). Every communication session between host
and CAT25080/160 must be preceded by a high to low
transition and concluded with a low to high transition of
CAT25080/160 will accept any one of the six instruction
op-codes listed in Table 1 and will ignore all other
possible 8-bit combinations. The communication proto–
col follows the timing from Figure 1.
¯¯
the CS input.
¯¯¯
WP: The write protect input pin will allow all write
Table 1: Instruction Set
¯¯¯
operations to the device when held high. When WP
Instruction
WREN
WRDI
Opcode
Operation
pin is tied low and the WPEN bit in the Status
Register (refer to Status Register description, later in
this Data Sheet) is set to “1”, writing to the Status
Register is disabled.
0000 0110 Enable Write Operations
0000 0100 Disable Write Operations
0000 0101 Read Status Register
0000 0001 Write Status Register
0000 0011 Read Data from Memory
0000 0010 Write Data to Memory
RDSR
¯¯¯¯¯
¯¯¯¯¯
HOLD: The HOLD input pin is used to pause trans–
mission between host and CAT25080/160, without
having to retransmit the entire sequence at a later
WRSR
READ
¯¯¯¯¯
time. To pause, HOLD must be taken low and to
WRITE
resume it must be taken back high, with the SCK
input low during both transitions. When not used for
¯¯¯¯¯
pausing, the HOLD input should be tied to VCC,
either directly or through a resistor.
Figure 1. Synchronous Data Timing
t
CS
V
IH
CS
V
IL
t
t
CSH
CSS
V
V
IH
t
t
WL
SCK
SI
WH
t
IL
t
H
SU
V
IH
VALID IN
V
IL
t
RI
FI
t
t
V
t
t
HO
DIS
V
OH
HI-Z
HI-Z
SO
V
OL
Note: Dashed Line = mode (1, 1) - - - - - -
Doc. No. 1122 Rev. A
4
© 2006 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CATALYST [ CATALYST SEMICONDUCTOR ]
