PRODUCT SPECIFICATION
TMC22091/TMC22191
8
CVBS
CVBS
7-0
7-0
GHSYNC
GVSYNC
PXCK
GHSYNC
GVSYNC
PXCK
TMC22071
TMC22x91
LDV
LDV
GENLOCKING VIDEO DIGITIZER
DIGITAL VIDEO ENCODER
2
8
MICROPROCESSOR
INTERFACE
27009A
Figure 37. TMC22x91-to-TMC22071 Interface Circuit
Printed Circuit Board Layout
Microprocessor I/O Operations
Designing with high-performance mixed-signal circuits
demands printed circuits with ground planes. Overall system
performance is strongly influenced by the board layout.
Capacitive coupling from digital to analog circuits may
result in poor picture quality. Consider the following sugges-
tions when doing the layout:
Various CLUT Read/Write operations are shown in Table 17.
Each step in the table requires a CS pulse (falling edge fol-
lowed by a rising edge) to execute.
For Write operations, R/W and A must conform to setup
1-0
and hold timing with respect to the falling edge of CS. D
7-0
must meet setup and hold timing with respect to the rising
edge of CS. These timing relationships are illustrated in Fig-
ure 10. When writing data into an internal register (i.e.
CLUT Address Register) an extra CS falling edge is required
to transfer the input data to that register. This requirement is
usually accomplished by executing the next step in the
sequence. If there is no planned next step in the sequence,
executing a Control Register Read step will meet the require-
ment and terminate the sequence.
• Keep analog traces (COMP, V ) as short and as
, R
far from all digital signals as possible.
REF REF
• The power plane for the TMC22x91 should be separate
from that which supplies other digital circuitry. A single
power plane should be used for all of the V
DD
pins. If the
power supply for the TMC22x91 is the same for the
system’s digital circuitry, power to the TMC22x91 should
be filtered with ferrite beads and 0.1µF capacitors to
reduce noise.
For Read operations, R/W and A must conform to setup
1-0
and hold timing with respect to the falling edge of CS. Read
• The ground plane should be solid, not cross-hatched.
Connections to the ground plane should be very short.
data on D is initiated by the falling edge of CS\ and termi-
7-0
• Decoupling capacitors should be applied liberally to V
pins. For best results, use 0.1µF capacitor in
DD
nated by the rising edge of CS as shown in Figure 11. When
reading Control Registers, valid data appears t
after the
DOM
parallel with 47µF capacitors. Lead lengths should be
falling edge of CS. When reading CLUT locations, an extra
CLUT Read step is needed to set up the CLUT Read
sequence. This is accomplished in the table by executing an
extra CLUT Read step just before the CLUT Read sequence
which returns successive d, e, and f data. CLUT Read
sequences must be terminated an extra CS falling edge. This
requirement is usually accomplished by executing the next
I/O step. If there is no planned next step in the sequence,
executing a Control Register Read step will meet the require-
ment and terminate the sequence.
minimized. Ceramic chip capacitors are the best choice.
• The PXCK should be handled carefully. Jitter and noise
on this clock or its ground reference will translate to noise
on the video outputs. Terminate the clock line carefully to
eliminate overshoot and ringing.
53
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
