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TMC22091R0C 参数 Datasheet PDF下载

TMC22091R0C图片预览
型号: TMC22091R0C
PDF下载: 下载PDF文件 查看货源
内容描述: 数字视频编码器/分层引擎 [Digital Video Encoders/Layering Engine]
分类和应用: 商用集成电路编码器
文件页数/大小: 60 页 / 394 K
品牌: CADEKA [ CADEKA MICROCIRCUITS LLC. ]
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TMC22091/TMC22191  
PRODUCT SPECIFICATION  
Table 17. CLUT Read/Write Sequences  
Step  
R/W\  
A
1-0  
D
7-0  
Function  
Write Entire CLUT Starting at Address 00  
1
1
0
0
01  
01  
11  
11  
11  
•••  
11  
11  
11  
00  
00  
00  
Write 00 into CLUT Address Register.  
Write 00 into CLUT Address Register.  
d1 written into D, CLUT address 00.  
e1 written into E, CLUT address 00.  
f1 written into F, CLUT address 00.  
repeat steps 3, 4, 5 until CLUT is full.  
d256 written into D, CLUT address FF.  
e256 written into E, CLUT address FF.  
f256 written into F, CLUT address FF.  
Sequence termination.  
2
0
d1  
3
0
e1  
4
0
f1  
•••  
767  
768  
769  
770  
•••  
0
•••  
d256  
e256  
f256  
xx  
0
0
1
Write CLUT Location address  
1
2
3
4
5
0
0
0
0
1
01  
11  
11  
11  
00  
addr  
d1  
e1  
f1  
Write addr into the CLUT Address Register.  
d1 written into D, CLUT address addr.  
e1 written into E, CLUT address addr.  
f1 written into F, CLUT address addr.  
Sequence termination.  
xx  
Read CLUT Location address  
1
2
3
4
5
6
0
1
1
1
1
1
01  
11  
11  
11  
11  
00  
addr  
xx  
Write addr into the CLUT Address Register.  
Set up for CLUT Read sequence.  
d1 read from D, CLUT address addr.  
e1 read from E, CLUT address addr.  
f1 read from F, CLUT address addr.  
Sequence termination.  
d1  
e1  
f1  
xx  
Read CLUT Address Register Then Write  
1
2
3
4
5
6
7
8
9
1
0
0
0
1
0
0
0
1
01  
11  
11  
11  
01  
11  
11  
11  
00  
addr  
d1  
Read CLUT Address Register.  
d1 written into D, CLUT address addr.  
e1 written into E, CLUT address addr.  
f1 written into F, CLUT address addr.  
Read CLUT Address Register. (terminates Write sequence)  
d2 written into D, CLUT address addr+1.  
e2 written into E, CLUT address addr+1.  
f2 written into F, CLUT address addr+1.  
Sequence termination.  
e1  
f1  
addr+1  
d2  
e2  
f2  
xx  
54  
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