PRODUCT SPECIFICATION
TMC22091/TMC22191
Switching Characteristics
Parameter
Conditions
Min.
Typ.
Max.
Units
PIPES
Pipeline Delay3
PD to Analog Out
44
44
44
PXCK
periods
t
t
t
t
t
Output Delay, CS to low-Z
6
23
ns
ns
ns
ns
ns
DOZ
Output Delay, CS to Data Valid4
Output Hold Time, CS to hi-Z
Output Delay, TCK to TDO Valid
100
DOM
HOM
DOTP
HOTP
10
30
25
Output Hold Time, TCK to TDO
Valid
5
t
Output Delay
PXCK to VHSYNC,
VVSYNC, PDC
ns
DOS
t
t
t
D/A Output Current Risetime
D/A Output Current Falltime
Analog Output Delay
10% to 90% of full-scale
90% to 10% of full-scale
2
ns
ns
ns
R
2
F
20
DOV
Notes:
1. Timing reference points are at the 50% level.
2. Analog C < 10 pF, D load < 40 pF.
LOAD 7-0
3. Pipeline delay, with respect to PXCK, is a function of the phase relationship between the internally generated PCK (PXCK/2)
and PXCK, as established by the hardware reset.
4. t
DOM
= 1 PXCK + 54 ns = 100 ns worst-case at PXCK = 24.54 MHz.
System Performance Characteristics
Parameter
Conditions
Min.
Typ.
Max.
10
Units
Bits
RES
ELI
ELD
EG
D/A Converter Resolution
10
10
Integral Linearity Error
Differential Linearity Error
Gain Error
0.25
0.20
±10
%
%
% FS
degree
dp
Differential Phase
PXCK = 24.54 MHz,
40 IRE Ramp3
0.5
0.9
dg
Differential Gain
PXCK = 24.54 MHz,
40 IRE Ramp3
%
SKEW
PSRR
CHROMA to LUMA Output Skew
Power Supply Rejection Ratio
0
2
ns
CCOMP = 0.1 µF, f = 1kHz
0.5
%/
%VDD
Notes:
1. TTL input levels are 0.0 and 3.0 Volts, 10%-90% rise and fall times <3 ns.
2. Analog C
3. NTSC
< 10 pF, D load < 40 pF.
7-0
LOAD
51
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
