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TMC22091R0C 参数 Datasheet PDF下载

TMC22091R0C图片预览
型号: TMC22091R0C
PDF下载: 下载PDF文件 查看货源
内容描述: 数字视频编码器/分层引擎 [Digital Video Encoders/Layering Engine]
分类和应用: 商用集成电路编码器
文件页数/大小: 60 页 / 394 K
品牌: CADEKA [ CADEKA MICROCIRCUITS LLC. ]
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TMC22091/TMC22191  
PRODUCT SPECIFICATION  
Control Register Definitions (continued)  
Standards Control Register (0F)  
7
6
5
4
3
2
1
0
EFEN  
SIX25  
PALID  
SETUP  
YGAIN  
CGAIN  
Reg  
Bit  
7
Name  
EFEN  
SIX25  
Function  
0F  
0F  
Same as Register 0E bit 7, but read-only.  
6
Select 625 lines per frame. When HIGH, the encoder assumes 625 line per  
frame. When LOW, 525 lines per frame are assumed.  
0F  
0F  
0F  
5
PALID  
SETUP  
YGAIN  
PAL select. When HIGH, Phase alternate line (PAL) operation is selected.  
When LOW, operation conforms to NTSC standards.  
4
Setup enable. When HIGH, a 7.5 IRE Pedestal is added to the output video.  
when LOW, no pedestal is added.  
3-2  
Luminance gain settings are adjusted to conform to the following NTSC and  
PAL standards:  
0 0 NTSC without SETUP  
0 1 NTSC-A and PAL-M  
1 0 PAL-I and PAL-N  
1 1 Reserved  
0F  
1-0  
CGAIN  
Chrominance gain settings are adjusted to conform to the following NTSC and  
PAL standards:  
0 0 NTSC without SETUP  
0 1 NTSC-A and PAL-M  
1 0 PAL-I and PAL-N  
1 1 Reserved  
Timing Registers (10-17)  
Reg  
Bit  
Name  
Function  
10  
7-0  
SY  
Horizontal sync tip length. This 8-bit register holds a value extending from 0 to  
255 PCK cycles.  
11  
12  
13  
14  
7-0  
7-0  
7-0  
7-0  
BR  
Breezeway length. This 8-bit register holds a value extending from 0 to 255  
PCK cycles.  
BU  
Burst length. This 8-bit register holds a value extending from 0 to 255 PCK  
cycles.  
CBP  
XBP  
Color back porch length. This 8-bit register holds a value extending from 0 to  
255 PCK cycles.  
Extended color back porch 8 LSBs. This 8-bit register holds the LSBs of a  
10-bit value extending from 0 to 1023 PCK cycles. The two MSBs are located in  
control register 18.  
15  
16  
17  
7-0  
7-0  
7-0  
VA  
VC  
VB  
Active video 8 LSBs. This 8-bit register holds the LSBs of a 10-bit value  
extending from 0 to 1023 PCK cycles. The two MSBs are located in control  
register 18.  
Active video start 8 LSBs. This 8-bit register holds the LSBs of a 10-bit value  
which is the initial half active video length extending from 0 to 1023 PCK cycles.  
The two MSBs are located in control register 18.  
Active video end 8 LSBs This 8-bit register holds the LSBs of a 10-bit value  
which is the end half active video length extending from 0 to 1023 PCK cycles.  
The two MSBs are located in control register 18.  
20  
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