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TMC22091R0C 参数 Datasheet PDF下载

TMC22091R0C图片预览
型号: TMC22091R0C
PDF下载: 下载PDF文件 查看货源
内容描述: 数字视频编码器/分层引擎 [Digital Video Encoders/Layering Engine]
分类和应用: 商用集成电路编码器
文件页数/大小: 60 页 / 394 K
品牌: CADEKA [ CADEKA MICROCIRCUITS LLC. ]
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PRODUCT SPECIFICATION  
TMC22091/TMC22191  
Control Register Definitions (continued)  
Timing Register (18)  
7
6
5
4
3
2
1
0
XBP  
Bit  
VA  
VC  
VB  
Reg  
Name  
Function  
18  
7-6  
XBP  
Extended color back porch 2 MSBs. These two bits hold the MSBs of a 10-bit  
value extending from 0 to 1023 PCK cycles. The LSBs are located in control  
register 14.  
18  
18  
5-4  
3-2  
VA  
VC  
Active video 2 MSB. These two bits hold the MSBs of a 10-bit value extending  
from 0 to 1023 PCK cycles. The LSBs are located in control register 15.  
Active video start 2 MSBs. These two bits hold the MSBs of a 10-bit value which  
is the initial half active video length extending from 0 to 1023 PCK cycles. The  
LSBs are located in control register 16.  
18  
1-0  
VB  
Active video end 2 MSBs. These two bits hold the MSBs of a 10-bit value which  
is the end half active video length extending from 0 to 1023 PCK cycles. The  
LSBs are located in control register 17.  
Timing Registers (19-1E)  
Reg  
Bit  
Name  
Function  
19  
7-0  
FP  
Front porch length. This 8-bit register holds a value extending from 0 to 255  
PCK cycles.  
1A  
1B  
7-0  
7-0  
EL  
Equalization pulse LOW length. This 8-bit register holds a value from 0 to 255  
PCK cycles.  
EH  
Equalization pulse HIGH length. This 8-bit register holds a value extending from  
0 to 255 PCK cycles. This value, when added to 256 (or 512), determines the  
final pulse length in the range of 256 to 511 (or 767) PCK cycles.  
1C  
7-0  
SL  
Vertical sync LOW length. This 8-bit register holds a value from 0 to 255 PCK  
cycles. This value, when added to 256 (or 512), determines the final pulse  
length in the range of 256 to 511 (or 767) PCK cycles.  
1D  
1E  
7-0  
7-0  
SH  
Vertical sync HIGH length. This 8-bit register holds a value extending from 0 to  
255 PCK cycles.  
CBL  
Color bar length. This 8-bit register holds a value which is the length of each  
color bar displayed extending from 0 to 255 PCK cycles.  
Timing Register (1F)  
7
6
5
4
3
2
1
0
FIELD  
LTYPE  
Reg  
Bit  
Name  
Function  
1F  
7-5  
FIELD  
Field identification (read only). These three bits are updated 12 PXCK periods  
after each VHSYNC. They allow the user to determine field type on a  
continuous basis.  
1F  
4-0  
LTYPE  
Line type identification (read only). These five bits are updates 5 PXCK periods  
after each VHSYNC. They allow the user to determine line type on a continuous  
basis.  
21  
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