PRODUCT SPECIFICATION
TMC22091/TMC22191
Control Register Definitions (continued)
Interface Control Register (02)
7
6
5
4
3
2
1
0
VITSEN
SHCY
TBASE
SOUT
FBDIS
PDCDIR
FLDLK
Reg
Bit
Name
Function
02
02
02
7
VITSEN
VITS lines enable. When LOW, all UBB lines in the vertical interval are black
burst regardless of input data. When HIGH, all UBB lines in the vertical interval
become UVV active video and are dependent upon input data.
6
SHCY
Short-cycle test mode. When LOW, normal operation is enabled. when HIGH,
EH (equalization pulse HIGH length) and SL (vertical sync LOW length) are
shortened by 256.
5-4
TBASE
Time-base source select. These two bits set up the TMC22x91 for either
genlock or frame buffer control of timing. When bits 5 and 4 are:
0 0 the encoder counts out its own time-base from input clock PXCK.
0 1 the encoder locks to synchronizing signals from external genlock.
1 0 the encoder locks to synchronizing signals from frame buffer controller.
02
02
02
02
3
2
1
0
SOUT
Sync output mode select. When LOW, VHSYNC and VVSYNC output separate
horizontal and vertical sync pulses. When HIGH, composite sync (H and V) is
output on VVSYNC while horizontal sync is output on VHSYNC.
FBDIS
PDCDIR
FLDLK
Frame buffer signals enable. When LOW, VVSYNC and VHSYNC outputs to
frame buffer are enabled. When HIGH, VVSYNC and VHSYNC outputs to
frame buffer are disabled.
PDC master/slave select. When LOW, PDC is an output where the encoder is
requesting data from the frame buffer. When HIGH, PDC is an input, and
directs the encoder to accept data from the frame buffer.
Field lock select. When LOW, (in Slave mode) the encoder locks to each new
field. When HIGH, the encoder locks to field 1 only.
15
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