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TMC22091R0C 参数 Datasheet PDF下载

TMC22091R0C图片预览
型号: TMC22091R0C
PDF下载: 下载PDF文件 查看货源
内容描述: 数字视频编码器/分层引擎 [Digital Video Encoders/Layering Engine]
分类和应用: 商用集成电路编码器
文件页数/大小: 60 页 / 394 K
品牌: CADEKA [ CADEKA MICROCIRCUITS LLC. ]
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TMC22091/TMC22191  
PRODUCT SPECIFICATION  
Control Register Definitions (continued)  
Format Control Register (01)  
7
6
5
4
3
2
1
0
Reserved  
LCREN  
RAMPEN  
CB  
FORMAT  
INMODE  
Reg  
Bit  
Name  
Function  
Reserved.  
01  
01  
7
6
LCREN  
(TMC22191) Layering Control Register enable. When LOW, the Layering  
Control Register is not available and Key Control Register functions are  
enabled. In this mode, the TMC22191 functions like the TMC22091. When  
HIGH, the Layering Control Register takes the place of the Key Control  
Register and enables the layering functions. Data loaded into the Key or  
Layering Control Registers will remain but have a different meaning if this bit is  
changed.  
01  
01  
01  
5
RAMPEN  
CB  
Modulated ramp test. When LOW (normal), the TMC22x91 encodes and  
outputs video corresponding to input data. When RAMPEN and CB are both  
HIGH, an internally generated 40 IRE modulated ramp is produced, preempting  
input data.  
4
Color bar test. When HIGH (normal), the TMC22x91 encodes and outputs  
video corresponding to input data. When CB, RAMPEN, and Format Control  
Register bit 0 are LOW, internally generated color bars are produced,  
preempting input data.  
3-2  
FORMAT  
PD input format select. Two bits select RGB, GBR, or YC C input data.  
23-0 B R  
When bits 3 and 2 are:  
0 0 the CLUT output is interpreted as RGB and is converted to YC C .  
B
R
0 1 is reserved. Bits 3 and 2 must be 00 or 10 when the Layering Control  
Register is enabled (TMC22191).  
1 0 the CLUT output is interpreted as GBR, and is converted to YC C .  
B
R
1 1 the CLUT output is interpreted as YC C .  
B
R
01  
1-0  
INMODE  
PD  
input mode select. These two bits set up the TMC22x91 for either 444,  
422, 15-bit, or 8-bit input modes.  
23-0  
0 0 24-bit/pixel GBR, RGB, or YC C 444 data enters from PD  
B
R
23-0  
0 1 YC C 422 data enters from PD  
; C and C alternate from PD  
B
R
23-8  
R
B
15-8  
1 0 15-bit/pixel GBR or RGB data from PD  
14-0  
1 1 8-bit/pixel color indexed data enters from PD  
.
7-0  
Bits 1 and 0 must be 00, 01, or 11 when the Layering Control Register is  
enabled (TMC22191).  
14