TMC22091/TMC22191
PRODUCT SPECIFICATION
Table 3. Control Register Map
(continued)
Reg
07
08-0D
Misc. Control Register
0E
0E
0E
0E
0E
0E
0E
0E
0F
0F
0F
0F
0F
0F
7
6
5
4
3
2
1
0
7
6
5
4
3-2
1-0
EFEN
COMPD/A
SVIDD/A
FKREN
RATIO
TFLK
T512
CB100
EFEN
SIX25
PALID
SETUP
YGAIN
CGAIN
Register 0E and 0F
enable
COMPOSITE D/A
disable
LUMA/CHROMA D/A
disable
Luminance processing
enabled
Luminance ratio select
Luminance pass
threshold select
EH/SL offset select
NTSC/PAL Color Bars
Bit
7-0
Name
FKEY
Function
Red/blue/C
R
data key
value
Reserved
Table 3. Control Register Map
(continued)
Reg
19
1A
1B
1C
1D
1E
1F
1F
20
21
22
23
24
25
26
27
28-3F
Test I/O Register
40
7-0
7-0
7-0
TESTDAT
MASK
Y
Test data input/output
Mask register
Y-component input/
output
Mask Register
50
60
Y-Component Register
Bit
7-0
7-0
7-0
7-0
7-0
7-0
7-5
4-0
7-0
7-0
7-0
7-0
7-0
7-0
7-0
7-0
Name
FP
EL
EH
SL
SH
CBL
FIELD
LTYPE
FREQL
FREQ3
FREQ2
FREQM
SYSPHL
SYSPHM
BURPHL
BURPHM
Function
Front porch length
Equalization pulse LOW
length
Equalization pulse HIGH
length
Vertical sync LOW
length
Vertical sync HIGH
length
Color bar length
Field identification
Line type identification
Subcarrier frequency 4th
byte (LSBs)
Subcarrier frequency 3rd
byte
Subcarrier frequency
2nd byte
Subcarrier frequency 1st
byte (MSBs)
Video phase offset LSBs
Video phase offset
MSBs
Burst phase offset LSBs
Burst phase offset MSBs
Reserved
Subcarrier Registers
Standards Control Register
Same as Reg 0E bit 7
but read-only
625/525 line per frame
select
Phase alternate line
select
7.5 IRE Pedestal Enable
Luminance gain settings
Chrominance gain
settings
Horizontal sync tip
length
Breezeway length
Burst length
Color back porch length
Extended color back
porch 8 LSB
Active video 8 LSB
Active video start 8 LSB
Active video end 8 LSB
Extended color back
porch 2 MSB
Active video 2 MSB
Active video start 2 MSB
Active video end 2 MSB
Timing Registers
10
11
12
13
14
15
16
17
18
18
18
18
7-0
7-0
7-0
7-0
7-0
7-0
7-0
7-0
7-6
5-4
3-2
1-0
SY
BR
BU
CBP
XBP
VA
VC
VB
XBP
VA
VC
VB
Notes:
1. Functions are listed in the order used for reading and
writing.
2. For each register listed above, all bits not listed are
reserved and should be set to zero to ensure proper
operation.
3. The meaning of Register 04 (Key Control Register/Layer-
ing Control Register) is determined by Format Control
Register bit 6 (TMC22191).
12
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
