ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)
1
25 °C
Supply Voltages
AV
DD
...................................................................... +6 V
DV
DD
..................................................................... +6 V
OV
DD
..................................................................... +6 V
Input Voltages
Analog Input ................................. –0.7 V to V
DD
+0.7 V
CLK Input ............................................................... V
DD
AV
DD
– DV
DD
.................................................. ±100 mV
AGND – DGND .............................................. ±100 mV
Output
Digital Outputs .................................................... 10 mA
Temperature
Operating Temperature ........................... –40 to +85 °C
Junction Temperature ...................................... +175 °C
Lead Temperature, (soldering 10 seconds) ...... +300 °C
Storage Temperature ............................ –65 to +150 °C
Note 1: Operation at any Absolute Maximum Rating is not implied. See
Electrical Specifications for proper nominal applied conditions
in typical applications.
ELECTRICAL SPECIFICATIONS
T
A
=T
MIN
to T
MAX
, V
DD
=+5.0 V, ƒ
S
=28 MSPS, V
IN
=0 to 4 V, V
RHS
=4.0 V, V
RLS
=0.0 V, unless otherwise specified.
PARAMETERS
Resolution
DC Accuracy
Integral Linearity Error (ILE)
Differential Linearity Error (DLE)
No Missing Codes
Analog Input
Input Voltage Range
Input Capacitance
Input Bandwidth
Input Impedance
–Full-Scale Error
1
+Full-Scale Error
1
Conversion Characteristics
Maximum Conversion Rate
Minimum Conversion Rate
Pipeline Delay (Latency)
Aperture Delay Time (T
AP
)
Aperture Jitter Time
Clock Duty Cycle
Over-Voltage Recovery Time
2
Reference Input
Resistance
Voltage Range
3
V
RHS
V
RLS
V
RHS
– V
RLS
Dynamic Performance
Effective Number of Bits
ƒ
IN
= 3.58 MHz
ƒ
IN
= 10 MHz
1
2
TEST
CONDITIONS
TEST
LEVEL
MIN
12
SPT7937
TYP
MAX
UNITS
Bits
V
V
VI
VI
V
V
V
V
VI
V
IV
V
V
V
28
1
V
RLS
±1.75
±0.9
Guaranteed
V
RHS
5.0
250
35
1.0
0.12
LSB
LSB
V
pF
MHz
kΩ
LSB
%FS
MHz
MHz
Clock Cycles
ns
ps (RMS)
%
ns
Ω
V
V
V
14
1.0
5.0
40
60
36
500
650
V
DD
2.0
5.0
VI
IV
IV
V
350
3.0
0.0
1.0
4.0
V
VI
10.3
10.0
Bits
Bits
The full-scale range spans the reference ladder sense pins, V
RHS
and V
RLS
. Refer to the Voltage Reference section for discussion.
Due to internal architecture, over-voltage recovery time is less than one clock cycle (i.e., 25 ns at ƒ
CLK
= 40 MHz).
3
For optimum performance, the full-scale voltage range (V
RHS
–V
RLS
) should be between 3 V to 5 V.
SPT7937
2
3/5/02
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
