Figure 4 – Simplified Reference Ladder Drive Circuit
Without Force/Sense Circuit
+4.0 V
External
Reference
V
RHS
(+3.91 V)
ANALOG INPUT
V
IN
is the analog input. The input voltage range is from
V
RLS
to V
RHS
(typically 4.0 V) and will scale proportionally
with respect to the voltage reference. (See the Voltage
Reference section.)
The drive requirements for the analog inputs are very mini-
mal when compared to most other converters due to the
SPT7937’s extremely low input capacitance of only 5 pF
and very high input resistance in excess of 35 kΩ.
21 mV
R/2
R
R
R
R
R
R=30
W
(typ)
All capacitors are 0.01 µF
The analog input should be protected through a series re-
sistor and diode clamping circuit as shown in figure 5. To
prevent possible latch-up condition, the power supplies
must be powered up before the input is applied.
Figure 5 – Recommended Input Protection Circuit
R
V
RLS
(0.075 V)
V
RLF
(AGND)
0.0 V
50 mV
+V
AV
DD
R/2
D1
In cases in which wider variations in offset and gain can be
tolerated, V
Ref
can be tied directly to V
RHF
and AGND can
be tied directly to V
RLF
as shown in figure 4. Decouple
force and sense lines to AGND with a 0.01 µF capacitor
(chip cap preferred) to minimize high-frequency noise in-
jection. If this simplified configuration is used, the following
considerations should be taken into account:
The reference ladder circuit shown in figure 4 is a simpli-
fied representation of the actual reference ladder with
force and sense taps shown. Due to the actual internal
structure of the ladder, the voltage drop from V
RHF
to V
RHS
is not equivalent to the voltage drop from V
RLF
to V
RLS
.
Typically, the top side voltage drop for V
RHF
to V
RHS
will
equal:
V
RHF
– V
RHS
= 0.5% of (V
RHF
– V
RLF
) (typical),
and the bottom side voltage drop for V
RLS
to V
RLF
will
equal:
V
RLS
– V
RLF
= 1.25% of (V
RHF
– V
RLF
) (typical).
Figure 4 shows an example of expected voltage drops for
a specific case. V
REF
of 4.0 V is applied to V
RHF
and V
RLF
is
tied to AGND. A 21 mV drop is seen at V
RHS
(= 3.79 V) and
a 50 mV increase is seen at V
RLS
(= 0.050 V).
Buffer
47
W
D2
ADC
V
D1 = D2 = Hewlett Packard HP5712 or equivalent
CALIBRATION
The SPT7937 uses a user-transparent, auto-calibration
scheme to ensure 12-bit accuracy over time and tempera-
ture. Gain and offset errors are continually adjusted to
12-bit accuracy during device operation.
Upon powerup, the SPT7937 begins its calibration algo-
rithm. In order to achieve the calibration accuracy required,
the offset and gain adjustment step size is a fraction of a
12-bit LSB. Since the calibration algorithm is an over-
sampling process, a minimum of 10,000 clock cycles are
required. This results in a minimum calibration time upon
powerup of 357 µsec (for a 28 MHz clock). Once cali-
brated, the SPT7937 remains calibrated over time and
temperature.
Since the calibration cycles are initiated on the rising edge
of the clock, the clock must be continuously applied for the
SPT7937 to remain in calibration.
SPT7937
8
3/5/02
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
