Figure 6 – On-Chip Protection Circuit
V
DD
120
W
DIGITAL OUTPUTS
Analog
120
W
The digital outputs (D0–D12) are driven by a separate sup-
ply (OV
DD
) ranging from +3 V to +5 V. This feature makes it
possible to drive the SPT7937’s TTL/CMOS-compatible
outputs with the user’s logic system supply. The format of
the output data (D0–D11) is straight binary. (See table III.)
The outputs are latched on the rising edge of CLK.
Table III – Output Data Information
ANALOG INPUT
+F.S. + 1/2 LSB
+F.S. –1/2 LSB
+1/2 F.S.
+1/2 LSB
OUT OF RANGE
D12
1
0
0
0
1
OUTPUT CODE
D11–D0
1111 1111 1111
1111 1111 111Ø
ØØØØ ØØØØ ØØØØ
0000 0000
0000 0000
000Ø
0000
Pad
INPUT PROTECTION
All I/O pads are protected with an on-chip protection circuit
shown in figure 6. This circuit provides ESD robustness to
3.5 kV and prevents latch-up under severe discharge con-
ditions without degrading analog transition times.
0.0 V
(Ø indicates the flickering bit between logic 0 and 1).
OUT-OF-RANGE OUTPUT
The Out-of-Range Output (D12) is an indication that the
analog input signal is outside the full-scale input voltage
range by 1 LSB. When this condition occurs, D12 will
switch to logic 1. All other data outputs (D0 to D11) will
remain at logic 0 or 1 as long as D12 remains at logic 1.
CLOCK INPUT
The SPT7937 is driven from a single-ended TTL-input
clock. Because the pipelined architecture operates on the
rising edge of the clock input, the device can operate over
a wide range of input clock duty cycles without degrading
the dynamic performance.
EVALUATION BOARD
The EB7937 evaluation board is available to aid designers
in demonstrating the full performance of the SPT7937.
This board includes a reference circuit, clock driver circuit,
output data latches and an on-board reconstruction of the
digital data. An application note (AN7937) describing the
operation of this board, as well as information on the test-
ing of the SPT7937, is also available. Contact the factory
for price and availability.
SPT7937
9
3/5/02
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
