TTL DIGITAL OUTPUT LEVELS
The SPT7871 supports TTL and some CMOS logic levels.
(Refer to minimum high voltage level for selected digital parts
that will interface with the SPT7871.) It has single-ended outputs
that are driven off a separate +5 V digital supply (DV
CC
).
adequate thermal performance under laboratory tests. Air
flow may be required for operation at elevated ambient
temperature. CADEKA recommends that the junction tem-
perature be maintained under +150
°C.
The thermal impedance values for the cerquad package are
θ
JC
= 3.3
°C/W
and
θ
JA =
70
°C/W
(junction to ambient in still
air with no heat sink).
Figure 3 - Clock Input Equivalent Circuit
AVCC
THERMAL MANAGEMENT
CADEKA recommends that a heat sink be used for this device
to ensure rated performance. A heat sink in still air provides
Figure 2 - Typical Interface Circuit
AGND
-A5.2
+A5
FB2
FB3
(ESD)
(ESD)
26 kΩ
6 kΩ
NCLK
*
*
.01
DGND DVCC
D10
CLK
26 kΩ
52 kΩ
(ESD)
-1.3 V
VEE AGND AVCC
(ESD)
Analog
Input
.01
V
IN
V
T
.01
V
M
.01
V
B
D9
D8
D7
D6
SPT7871
D5
D4
D3
D2
Interfacing
Logics
VEE
Figure 4 - Digital Outputs Equivalent Circuit
DVCC
ECL
Differential
Clock Input
X
X
CLK
CLK
M
INV
L
INV
D1
D0
(ESD)
FB1
+A5
+D5
-A5.2
10µF
10 µF
+
+D5
10 µF
+
Notes:
1)
X
= Line termination
2)
+A5
TTL OUT
*
= 0.01 µF chip cap. in parallel with
2.2 µF, tant cap.
+
(ESD)
AGND
-5.2 V
DGND
+5V
3) Immediate output buffer is highly recommended
+5 V
to optimize the performance due to reflection.
DGND
PACKAGE OUTLINE
44L Cerquad
INCHES
SYMBOL
A
B
C
44
MILLIMETERS
MAX
0.709
0.041
MIN
13.97 typ
17.40
0.94
0.41 typ
0.20 typ
0.051
0.150
0.69
0.15 typ
2.03
3.81
1.30
18.00
1.04
MAX
MIN
0.550 typ
0.685
0.037
0.016 typ
0.008 typ
0.027
0.006 typ
0.080
D
E
F
G
H
C
1
D
A
B
0 - 5°
H
E
F
G
A
B
SPT7871
7
9/7/98
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
