ANALOG INPUT
The SPT7871 has a single-ended analog input with a bipolar
input range from -1 V to +1 V. The bipolar input allows for
easier interface by external op amps when compared to
unipolar input devices. Because the input common mode is
0 V, the external op amp can operate without a voltage offset
on the output, thereby maximizing op amp head room and
minimizing distortion.
In addition, the 0 V common mode allows for a very simple DC
coupled analog input connection if desired. The current drive
requirements for the analog input are minimal when com-
pared to conventional flash converters due to the SPT7871’s
low input capacitance of only 5 pF and very high input
impedance of 150 kΩ.
CLOCK INPUTS
The clock inputs are designed to be driven differentially
with ECL levels.
For optimal noise performance, the clock
input rise time should be a maximum of 1.5 ns. Because of
this, the use of
fast
logic is recommended. The analog input
signal is latched on the rising edge of the CLK.
The clock may be driven single-ended since the NCLK pin is
internally biased to -1.3 V. NCLK may be left open but a
.01
µF
bypass capacitor from NCLK to AGND is recom-
mended. NOTE: System performance may be degraded due
to increased clock noise or jitter.
The performance of the SPT7871 is specified and tested with
a 50% clock duty cycle. However, at sample rates greater
than 80 MSPS, additional gains in the dynamic performance
of the device may be obtained by adjusting the clock duty
cycle. Typically, operation near 55% duty cycle will yield
improved results.
INTERNAL VOLTAGE REFERENCE
The SPT7871 incorporates an on-chip voltage reference.
The top and bottom reference voltages are each internally
tied to their respective top and bottom of the internal refer-
ence ladder. The pins for the voltage references and the
ladder (including the center of the ladder) are brought out to
pins on the device for decoupling purposes only (pins V
T,
V
M,
and V
B
). A .01
µF
capacitor should be used on each pin and
tied to AGND. See the typical interface circuit (figure 2).
The internal voltage reference and the internal error correc-
tion logic eliminate the need for driving externally the voltage
reference ladder. In fact,
the voltage reference ladder should
not be driven
with an external voltage reference source as the
internal error correction circuitry already compensates for the
internal voltage and no improvement will result.
available and are controlled by the MINV and LINV pins.
Table III shows the four possible output formats possible as
a function of MINV and LINV. Table II shows the output coding
data format versus analog input voltage relationship.
Table II - Output Coding Data Format
V
IN
>+1.0 V
(+FS)
+1.0 V -1 LSB
0.0 V
-1.0 V +1 LSB
(-FS)
<-1.0 V
D10
1
0
0
0
0
0
0
0
D9…D0 (Binary*) D9…D0 (2's Comp*)
11 1111 1111
01 1111 1111
11 1111 1111
01 1111 1111
11 1111 1110
10 0000 0000
01 1111 1111
00 0000 0001
00 0000 0000
00 0000 0000
01 1111 1110
00 0000 0000
11 1111 1111
10 0000 0001
10 0000 0000
10 0000 0000
*Refer to table III for possible output formats.
OVERRANGE BIT - D10
D10 is the overrange bit which is asserted whenever the
analog input signal exceeds the positive full scale input by
1 LSB. When this condition occurs the D10 bit will be asserted
to logic high and remain high continuously until the overrange
condition is removed from the input.
All other output signals will also stay at their maximum
encoded output throughout this condition. D10 is not as-
serted for an underscale condition when the input exceeds
the negative full scale.
DIGITAL OUTPUT DATA TIMING
The data is presented on the output pins two clock cycles after
the input is sampled with an additional output delay of
typically 3 ns. The data is held valid for one clock cycle. Refer
to the timing diagram shown in figure 1.
DIGITAL OUTPUT CONTROL PINS - MINV, LINV
Two digital output control pins control the digital output
format. See table III. The MINV pin is a CMOS/TTL-compat-
ible input. It inverts the most-significant bit (D9) when tied to
+5 V. The most-significant bit (D9) is noninverted when MINV
is tied to ground or floated. The MINV pin is internally pulled
down to ground.
The LINV pin is a CMOS/TTL-compatible input. It inverts the
least-significant bits (D8 through D0) when tied to +5 V. The
least-significant bits (D8 through D0) are noninverted when
LINV is tied to ground or floated. The LINV pin is internally
pulled down to ground.
Table III - Data Output Bits
MINV
0V
0V
+5 V
+5 V
LINV
0V
+5 V
0V
+5 V
Description of Data
Binary (Noninverted)
Two's Complement (Inverted)
Two's Complement (Noninverted)
Binary (Inverted)
DIGITAL OUTPUTS
DIGITAL OUTPUT DATA FORMAT - D0 - D9
D0 is the least-significant bit for the digital data output, and D9
is the most-significant bit. Four data output formats are
SPT7871
5
9/7/98
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
