Figure 1 - Timing Diagram
N
tclk
tpwh
tpwl
N+1
N+2
CLK
t
d
OUTPUT
DATA
N-3
N-2
DATA VALID
N-1
DATA VALID
N
Table I - Data Output Timing Parameters
Timing Parameter
f
clock
Clock Pulse Width High (t
pwh
)
Clock Pulse Width Low (t
pwl
)
Switching Delay (t
d
)
Clock Latency
Minimum
2 MHz
4.0 ns
4.0 ns
3 ns
2 clock cycles
resultant 10-bit data conversion is internally latched and
presented on the data output pins via buffered output drivers.
Typical
Maximum
100 MHz
250 ns
250 ns
THEORY OF OPERATION
The SPT7871 uses a two stage subranging architecture
incorporating a 3-bit flash MSB conversion stage followed by
an 8-bit interpolating folder conversion stage. Digital error
correction logic combines the results of both stages to pro-
duce a 10-bit data conversion digital output.
The analog signal is input directly to the 3-bit flash converter
which performs a 3-bit conversion and in turn drives an
internal DAC used to set the second stage voltage reference
level. The 3-bit result from the flash conversion is input to the
digital error correction logic and used in calculation of the
upper most significant bits of the data output.
The analog input is also input directly to an internal track-and-
hold amplifier. The signal is held and amplified for use in the
second stage conversion. The output of the track-and-hold is
input into a summing junction that takes the difference
between the track-and-hold amplifier and the 3-bit DAC
output. The residual is captured by a second track-and-hold
which holds and amplifies this residual voltage.
The residual held by the track-and-hold amplifier is input to an
8-bit interpolating folder stage for data conversion. The 8-bit
converted data from the folder stage is input into the digital
error correction logic and used in calculation of the lower
significant bits.
The error correction logic incorporates a proprietary scheme
for compensation of any internal offset and gain errors that
might exist to determine the 10-bit conversion result. The
TYPICAL INTERFACE CIRCUIT
The SPT7871 requires few external components to achieve
the stated operation and performance. Figure 2 shows the
typical interface requirements when using the SPT7871 in
normal circuit operation. The following section is a description
of the pin functions and outlines critical performance criteria
to consider for achieving the optimal device performance.
POWER SUPPLIES AND GROUNDING
The SPT7871 requires the use of three supply voltages: V
EE,
AV
CC
and DV
CC
. The V
EE
and AV
CC
supplies should be
treated as analog supply sources. This means the V
EE
and
V
CC
ground returns of the device should both be connected
to the analog ground plane. Each power supply pin should be
bypassed as closely as possible to the device with .01
µF
and
2.2
µF
capacitors as shown in figure 2.
The two grounds available on the SPT7871 are AGND and
DGND. DGND is used only for TTL outputs and is to be
referenced to the output pullup voltage. These grounds are
not tied together internal to the device. The use of ground
planes is recommended to achieve the best performance of
the SPT7871. The AGND and the DGND ground planes
should be separated from each other and only connected
together at the device through an inductance or ferrite bead.
Doing this will minimize the ground noise pickup.
SPT7871
4
9/7/98
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
