ELECTRICAL SPECIFICATIONS
T
A
= +25
°C
, DV
CC
=AV
CC
= +5.0 V, V
EE
= -5.2 V, V
IN
=
±1.0
V, f
clock
= 80 MHz, 50% clock duty cycle, unless otherwise specified.
PARAMETERS
MIN
TYP
MAX
Dynamic Performance
Signal-to-Noise + Distortion (SINAD)
f
IN
=10 MHz
I
51
53
f
IN
= 25 MHz
I
51
53
f
IN
= 25 MHz
f
clock
= 100 MHz
V
50
f
IN
= 50 MHz
I
47
49
f
IN
= 50 MHz
f
clock
= 100 MHz
V
47
Spurious Free Dynamic Range
f
IN
= 10 MHz
V
65
f
IN
= 25 MHz
V
63
f
IN
= 50 MHz
V
52
2
Two-Tone IMD Rejection
V
-65
Differential Phase
V
0.5
Differential Gain
V
1
Power Supply Requirements
AV
CC
Supply Voltage
IV
4.75
5.0
5.25
DV
CC
Supply Voltage
IV
4.75
5.0
5.25
V
EE
Supply Voltage
IV
-4.95
-5.2
-5.45
V
CC
Supply Current
Full Temperature
VI
210
248
V
EE
Supply Current
Full Temperature
VI
128
151
Power Dissipation
Full Temperature
VI
1.7
2.0
Power Supply Rejection Ratio
IV
30
Digital Inputs
LINV, MINV
V
CMOS/TTL
Clock Inputs
Logic 1 Voltage (ECL)
VI
-1.1
Logic 0 Voltage (ECL)
VI
-1.5
Maximum Input Current Low
VI
-100
+100
Maximum Input Current High
VI
-100
+100
Pulse Width Low (CLK)
IV
4.0
250
Pulse Width High (CLK)
IV
4.0
250
Rise/Fall Time
20% to 80%
IV
1.5
Digital Outputs
Logic 1 Voltage (TTL)
2 mA
VI
2.4
2.8
Logic 0 Voltage (TTL)
2 mA
VI
0.5
0.8
t
Rise
10% to 90%
V
2.0
t
Fall
10% to 90%
V
2.0
1
2048 pt FFT using distortion harmonics 2 through 10.
2
Measured as a second order (f1-f2) intermodulation product from a two-tone test with each input tone at 0 dBm.
TEST
CONDITIONS
TEST
LEVEL
UNITS
dB
dB
dB
dB
dB
dB FS
dB FS
dB FS
dBc
Degree
%
V
V
V
mA
mA
W
dB
Logic
V
V
µA
µA
ns
ns
ns
V
V
ns
ns
TEST LEVEL CODES
All electrical characteristics are subject to the
following conditions:
All parameters having min/max specifications
are guaranteed. The Test Level column indi-
cates the specific device testing actually per-
formed during production and Quality Assur-
ance inspection. Any blank section in the data
column indicates that the specification is not
tested at the specified condition.
Unless otherwise noted, all tests are pulsed
tests; therefore, T
J
= T
C
= T
A
.
TEST LEVEL
I
II
III
IV
V
VI
TEST PROCEDURE
100% production tested at the specified temperature.
100% production tested at T
A
= +25
°C,
and sample
tested at the specified temperatures.
QA sample tested only at the specified temperatures.
Parameter is guaranteed (but not tested) by design
and characterization data.
Parameter is a typical value for information purposes
only.
100% production tested at T
A
= +25
°C.
Parameter is
guaranteed over specified temperature range.
SPT7871
3
9/7/98
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
