DIGITAL OUTPUTS: D0 TO D6, DR, NDR (A AND B)
The digital outputs can drive 50
Ω
to ECL levels when
pulled down to –2 V. When pulled down to –5.2 V, the out-
puts can drive 130
Ω
to 1 kΩ loads. CADEKA recommends
SPT7610 TEST MODE FUNCTION: TEST PIN
using differential receivers on the outputs of the data
The SPT7610 supports a special test mode function that
ready lines to ensure the proper output rise and fall times.
overrides the SPT7610’s internal data output latch stage
BINARY AND TWO’S COMPLEMENT OUTPUT:
and exercises the digital outputs in an alternating test pat-
MINV, LINV
tern. This enables the user to test digital interface logic
downstream from the SPT7610 with a known set of digital
Control pins are provided that enable selection of one of
test patterns.
four digital output formats. (Table I shows selection of
these output formats as a function of the MINV and LINV Test mode pin 3 controls the SPT7610 mode of operation
pins.) When the MINV pin is high, the MSB output is in- such that when it is low, the SPT7610 operates in normal
verted and when it is low, the it is noninverted. Likewise, mode. When test mode pin 3 is brought high, the
when the LINV pin is high, the LSB output is inverted and SPT7610 will begin to output test pattern 1 (table II) on the
when it is low, the it is noninverted. The user can select next rising edge of the clock. (See figure 2.) It will output
either binary, inverted binary, two’s complement or the test patterns alternating between test pattern 1 and
inverted two’s complement digital output format.
test pattern 2 as long as test mode pin 3 is held high. The
minimum set-up time (t
su
) can be as low as 0 nsec.
REFERENCE INPUTS: V
RBF
, V
RBS
, V
R1
, V
RM
,
V
R3
, V
RTF
, V
RTS
Only the digital output stage is involved in the test mode
operation. All ADC stages before the digital output stage
There are two reference inputs and three external refer-
continue normal data conversion operation while the test
ence voltage taps. These are –1.0 V V
RBF
(bottom force)
mode is active. When test mode pin 3 is brought back low,
and V
RBS
(bottom sense), –0.75 V V
R1
(1/4 tap), –0.5 V
the SPT7610 will resume output of valid data on the next
V
RM
(mid-point tap), –0.25 V V
R3
(3/4 tap) and 0.0 V
rising edge of the clock. The valid data output will corre-
(AGND) V
RTF
(top force) and V
RTS
(top sense). The top ref-
spond to a two-clock-cycle pipeline delay as shown in
erence pin is normally tied to analog ground (AGND) and
figure 2.
the bottom reference pin can be driven by an op amp as
Table II – SPT7610 Test Mode Output Bit Patterns
shown in figure 3.
The reference voltage taps can be used to control integral
linearity over temperature. The mid-point reference tap
(V
RM
) is normally driven by an op amp to insure tempera-
ture stable operation or may be bypassed for limited tem-
perature operation. The 1/4 (V
R1
) and 3/4 (V
R3
) reference
Table I – Output Coding Table
TRUE
MINV=LINV=0
ANALOG INPUT VOLTAGE
–1 V + 1/2 LSB
D6
0
0
–0.5 V
0
D
5
_______D
0
0 0 0 0 0 0
0 0 0 0 0 1
0111111
1 0 0 0 0 0
0 V – 1/2 LSB
0
1
0V
1
Tie
ladder taps are typically bypassed to add noise suppres-
sion as shown in figure 3 or may be driven with op amps to
adjust integral linearity.
D6
Test Pattern 1
Test Pattern 2
1
0
D5
0
1
D4
1
0
D3
0
1
D2
1
0
D1
0
1
D0
1
0
BINARY
INVERTED
TWOs COMPLEMENT
TRUE
INVERTED
MINV=LINV=1 MINV=1; LINV=0 MINV=0; LINV=1
D
5
______D
0
1 1 1 1 1 1
1 1 1 1 1 0
1 0 0 0 0 0
0 1 1 1 1 1
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
D
5
______D
0
1000000
1000001
1 1 1 1 1 1
0 0 0 0 0 0
0 1 1 1 1 1
0 1 1 1 1 1
0 1 1 1 1 1
D
5
______D
0
0111111
0111110
0 0 0 0 0 0
1 1 1 1 1 1
1 0 0 0 0 0
1 0 0 0 0 0
1 0 0 0 0 0
1 1 1 1 1 1
1 1 1 1 1 1
1 1 1 1 1 1
1
MINV/LINV to GND for logic 1.
2
Float MINV/LINV for logic 0. (MINV/LINV are internally pulled down to –5.2 V.)
SPT7610
7
1/21/02
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
