Figure 3 – Typical Interface Circuit
V
IN
**
50
W
V
IN
V
IN
DRB
DRB
DRA
V
RTF
R
V
RTS
DRA
DRB (DATA READY)
DRB (DATA READY)
DRA (DATA READY)
DRA (DATA READY)
D6B (OVR)
D5B (MSB)
D4B
D3B
D2B
D1B
D0B (LSB)
D6A (OVR)
D5A (MSB)
D4A
D3A
D2A
D1A
D0A (LSB)
+
R
2.0 V
Reference
Convert
U1
22
W
*
*
*
V
R3
V
RM
V
R1
V
RBS
V
RBF
50
W
50
W
SPT7610
U1
22
W
2N2907
5.2 V
U2
AGND
DGND
AV
EE
TYPICAL INTERFACE CIRCUIT
The typical interface circuit is shown in figure 3. External
reference taps are provided for correcting integral
nonlinearity errors. These taps can be actively driven to
reduce these errors. (See the Reference Inputs discus-
sion below.) The SPT7610 evaluation board application
note contains more details on interfacing the SPT7610.
The function of each pin and external connections to other
components is as follows:
POWER SUPPLY PINS: AV
EE
, AGND, DGND
AV
EE
is the supply pin with AGND as ground for the de-
vice. The AV
EE
power supply pin should be bypassed as
close to the device as possible with a 10 µF tantalum ca-
pacitor, in parallel with 100 pF and .01 µF chip capacitors.
Place the 100 pF chip capacitor closest to the SPT7610.
Digital ground (DGND) is the ground for the ECL outputs
and is to be referenced to the output pulldown voltage and
appropriately bypassed as shown in figure 3.
+
*
5.2 V
CLK
NCLK
50
W
50
W
MINV
LINV
Test
5.2 V
5.2 V
5.2 V
.1 µF
FB = Ferrite bead
2.0 V
Pulldown
(Digital)
U1 = TLV2464 or equivalent with low offset/noise.
R = 1 kW; 0.05% matched or better
= AGND
2 V
Pulldown
(Analog)
5.2 V
*
FB
= DGND
U2 = Motorola ECLinPS Lite, MC10EL16, differential receiver.
*
= 2.2 µF Tantalum Capacitor, 0.1 µF and 100 pF chip capacitors.
** = Care must be taken to avoid exceeding the maximum rating
for the input, especially during power up sequencing of the
analog input driver.
ANALOG INPUT: V
IN
There are two analog input pins that are tied to the same
point internally. Either one may be used as an analog input
sense and the other for input force. This is convenient for
testing the source signal to see if there is sufficient drive
capability. The pins can also be tied together and driven by
the same source. The SPT7610 is superior to similar de-
vices due to a preamplifier stage before the comparators.
This makes the device easier to drive because it has con-
stant capacitance and induces less slew rate distortion.
CLOCK INPUTS: CLK, NCLK
The clock inputs are designed to be driven differentially
with ECL levels. The duty cycle of the clock should be kept
at 50% to avoid causing larger second harmonics. If this is
not important to the intended application, then duty cycles
other than 50% may be used.
SPT7610
6
1/21/02
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
