Figure 1 – Timing Diagram
1 nsec
N+1
N+2
N+5
N+3
N+4
V
IN
N
CLK (1 GHz)
t
drA
DRA
DRA
N2
OutputA Skew
(t
oskA
)
t
odA
Data Bank A
N
DOADRA Delay
(t
odrA
)
N+2
t
odB
t
drB
DRB
DRB
Data Bank B
N3
OutputB Skew
(t
oskB
)
N1
N+1
DOBDRB Delay
(t
odrB
)
Figure 2 – Test Mode Timing Diagram
FIRST
POWER
RISING EDGE
ON
1
2
VIN
8
7
6
3
5
4
9
10
11
CLK IN
LOGIC LOW
TEST
ADC (Normal Operation)
t
su
TEST MODE
ADC (Normal Operation)
DRA
t
dr
NDRA
t
od
OUTPUT
BANK A
(DA0-6)
DRB
INVALID DATA
INVALID DATA
1
Bank A Test Pattern 1:
- Even Bits = Hi
- Odd Bits = Low
Bank A Test Pattern 2:
- Even Bits = Low
- Odd Bits = Hi
7
9
t
dr
NDRB
t
od
OUTPUT
BANK B
(DB0-6)
INVALID DATA
INVALID DATA
2
Bank B Test Pattern 1:
- Even Bits = Hi
- Odd Bits = Low
Bank B Test Pattern 2:
- Even Bits = Low
- Odd Bits = Hi
8
SPT7610
5
1/21/02
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
